CN-122002851-A - Semiconductor device and method for manufacturing the same

Abstract

A method of manufacturing a semiconductor device. According to some embodiments, the method includes forming a substrate of a first conductivity type having a doped layer formed therein that can be used as a bottom layer of a tub-like structure in the semiconductor device. The bottom layer has a second conductivity type opposite the first conductivity type, and the bottom layer has a peak doping concentration plane having a predetermined bottom layer buried depth from a top surface of an initial substrate layer of the substrate, the predetermined buried depth being substantially greater than 0.5 μm. The method may further include forming a plurality of sidewalls of the tub-like structure. The method may further include forming the tub-like structured high voltage transistor.

Inventors

• LIU ZHIXIN
• LIAN YANJIE
• FU DAPING

Assignees

• 成都芯源系统有限公司

Dates

Publication Date

20260508

Application Date

20251105

Priority Date

20241105

Claims (20)

1. 1. A method of manufacturing a semiconductor device, comprising: the method includes forming a substrate having a first conductivity type, forming a doped layer in the substrate for use as a bottom layer of a tub-like structure in the semiconductor device, the bottom layer having a second conductivity type opposite to the first conductivity type, and further forming a bottom layer peak dopant concentration plane of the bottom layer having a predetermined bottom layer buried depth from a top surface of an initial substrate layer of the substrate, the predetermined bottom layer buried depth being substantially greater than 0.5 μm.
2. 2. The method of claim 1, wherein the predetermined underlayer implant depth is substantially in the range of 1 μm to 5 μm.
3. 3. The method of claim 1, wherein forming the substrate further comprises forming a buried connection region in the substrate formed for each of the plurality of sidewalls of the tub-like structure, and the buried connection region is in contact with at least the bottom layer.
4. 4. The method of claim 3, wherein a buried depth of the underlayer in the substrate is greater than a buried depth of the buried connection region in the substrate.
5. 5. The method of claim 3, wherein the buried connection region is formed in the initial substrate layer and has a buried connection region peak doping concentration plane having a predetermined buried connection depth from a top surface of the initial substrate layer that is less than the predetermined bottom layer buried depth.
6. 6. The method of claim 5, wherein the predetermined bottom layer buried depth is substantially greater than the predetermined buried connection depth by 0.5 μm to 3.5 μm when measured relative to a top surface of the initial substrate layer.
7. 7. The method of claim 1, wherein forming the substrate comprises: providing the initial substrate layer having a first conductivity type; Implanting dopants of a second conductivity type, suitable and compatible with a high energy implantation process, into said initial substrate layer from a top surface thereof to form a first buried implant region at an implant plane having said predetermined substrate implant depth, and And executing a pushing process to diffuse the first buried injection region to form a bottom layer.
8. 8. The method of claim 7, wherein forming the substrate further comprises: Implanting dopants of a second conductivity type, which are suitable and compatible with a low energy implantation process, into said initial substrate layer from a top surface thereof, such that a second buried implant region is fabricated in the substrate layer for each of a plurality of sidewalls of said tub-like structure, wherein the second buried implant region is located at an implant plane having a predetermined buried connection depth, and The advancing process is shared such that the second buried implant region is diffused to form a buried connection region for each of a plurality of sidewalls of the tub-like structure.
9. 9. The method of claim 1, wherein forming the substrate further comprises: An epitaxial layer is formed on the initial substrate layer, wherein the thickness of the epitaxial layer is in the range of 8 μm to 16 μm.
10. 10. The method of claim 9, further comprising: A drift region of a second conductivity type is formed for each of a plurality of transistor cells of a high voltage transistor to be fabricated in the substrate.
11. 11. The method of claim 10, further comprising: a RESURF region of a first conductivity type is formed in the epitaxial layer for each of a plurality of transistor cells of the high voltage transistor.
12. 12. The method of claim 11, wherein RESURF regions of each of the plurality of transistor cells are buried doped regions buried in an epitaxial layer at a predefined RESURF buried depth.
13. 13. The method of claim 11, wherein the RESURF region of each of the plurality of transistor cells is a doped region extending from a top surface of a substrate into an epitaxial layer to a depth of a predefined RESURF depth.
14. 14. The method of claim 9, further comprising: A sidewall connection region of a second conductivity type is formed in the epitaxial layer for each of the plurality of sidewalls of the tub-like structure, wherein the sidewall connection region is a buried doped region buried in the epitaxial layer and having a predetermined sidewall connection depth.
15. 15. The method of claim 14, wherein forming the epitaxial layer comprises: forming a lower portion of an epitaxial layer on the initial substrate layer; Forming a sidewall connection region for each of a plurality of sidewalls at a lower portion of the epitaxial layer by a doping process, and An upper portion of the epitaxial layer is formed over a lower portion of the epitaxial layer.
16. 16. The method of claim 9, further comprising: A plurality of shallow trench isolation structures are formed at a plurality of predefined locations of the epitaxial layer.
17. 17. A method as in claim 3, further comprising: A well region of a second conductivity type is formed for each of the plurality of sidewalls, wherein the well region extends vertically downward into the substrate from a top surface of the substrate until it is in contact with or connected to the buried connection region.
18. 18. The method of claim 14, further comprising: A well region of a second conductivity type is formed for each of the plurality of sidewalls, wherein the well region extends vertically downward into the substrate from a top surface of the substrate until it is in contact with or connected to the sidewall connection region.
19. 19. The method of claim 10, further comprising: A body well region of a first conductivity type is formed for each of a plurality of transistor cells of the high voltage transistor to be fabricated in the substrate, wherein the body well region is located beside the drift region.
20. 20. The method of claim 10, further comprising: forming a gate region for each of a plurality of transistor cells of the high voltage transistor; forming a body region of a first conductivity type in the substrate for each of a plurality of transistor cells of the high voltage transistor, wherein the body region is separated from the drift region; Forming a source region and a drain region of a second conductivity type for each of a plurality of transistor cells of the high voltage transistor; Forming an extraction region for each of a plurality of sidewalls of the tub-like structure, the extraction region sharing the same formation process as the source region and the drain region, and A body contact region of a first conductivity type is formed for each of a plurality of transistor cells of the high voltage transistor.

Description

Semiconductor device and method for manufacturing the same Technical Field Embodiments of the present application relate generally to semiconductor devices and, more particularly, but not exclusively, to high voltage semiconductor devices and methods of manufacturing the same. Background Power transistors, such as high voltage Metal-Qxide Semiconductor (MOS) transistors, are widely used in a variety of power management scenarios, including power switching elements for use as power management devices in industrial and/or consumer electronic devices. In most high-current or high-power application fields such as notebook computers, servers, automobiles, and the like, transistors with high voltage resistance are required. Disclosure of Invention According to an embodiment of the present invention, there is provided a semiconductor device having a substrate of a first conductivity type, and a barrel-like structure of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. In one embodiment, the substrate includes an initial substrate layer of a first conductivity type, and an epitaxial layer of the first conductivity type formed on the initial substrate layer. In one embodiment, the tub-like structure includes a bottom layer of a second conductivity type embedded in the initial substrate layer. In one embodiment, the bottom layer has a peak doping concentration plane that is substantially greater than 0.5 μm in depth of burial relative to the top surface of the initial substrate layer. In one embodiment, the tub-like structure further comprises a plurality of sidewalls in contact with or connected to the bottom layer, each of the plurality of sidewalls extending downwardly from the substrate top surface to at least contact or connect with the bottom layer. In one embodiment, the semiconductor device further includes a transistor formed in the substrate and located in a portion of the tub-like structure. In one embodiment, the transistor has a breakdown voltage of more than 70V, even more particularly up to more than 100V. According to one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device has a substrate of a first conductivity type, and a tub-like structure of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. In one embodiment, the tub-like structure comprises a bottom layer and a plurality of sidewalls in contact with the bottom layer, and each of the plurality of sidewalls comprises a buried connection region, i.e. a first buried layer, the bottom layer comprising a second buried layer having a buried depth in the substrate that is greater than a buried depth of the buried connection region in the substrate when measured with reference to a top surface of the substrate. In one embodiment, the semiconductor device further includes a transistor formed within the tub-like structure. In one embodiment, the transistor has a breakdown voltage of more than 70V, even more particularly up to more than 100V. According to an embodiment of the present disclosure, there is also provided a method of manufacturing a semiconductor device. The method includes forming a substrate of a first conductivity type that includes a bottom layer of the tub-like structure. The bottom layer being of a second conductivity type opposite the first conductivity type and having a peak doping concentration plane having a predetermined bottom layer buried depth from a top surface of an initial substrate layer of the substrate, the predetermined buried depth being substantially greater than 0.5 μm. In one embodiment, the step of forming the substrate further comprises forming a buried connection region in the substrate for each of the plurality of sidewalls of the tub-like structure, and the buried connection region is in contact with at least the bottom layer. The buried depth of the bottom layer in the substrate is greater than the buried depth of the buried connection region in the substrate. In one embodiment, forming the substrate further comprises forming an epitaxial layer having a thickness in the range of 8 μm to 16 μm on the initial substrate layer. In one embodiment, the method further comprises forming a drift region of the second conductivity type for each of a plurality of transistor cells of a high voltage transistor to be fabricated in the substrate. In one embodiment, the method may optionally further comprise forming RESURF regions of the first conductivity type in the epitaxial layer for each of the plurality of transistor cells of the high voltage transistor. In one embodiment, the method may optionally further comprise forming a sidewall connection region of the second conductivity type in the epitaxial layer for each of the plurality of sidewalls of the tub-like structure. The sidewall connection region may be a buried doped regi