CN-122002852-A - Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a substrate of a first conductivity type and a barrel-like structure of a second conductivity type formed in the substrate. The second conductivity type is opposite the first conductivity type. The tub-like structure comprises a bottom layer of a second conductivity type embedded in an initial substrate layer of said substrate, the bottom layer having a peak doping concentration plane with a predetermined depth of implantation from a top surface of said initial substrate layer, the predetermined depth of implantation being substantially greater than 0.5 μm. The use of such tub-like structures helps to break through the technical bottlenecks of the prior art for manufacturing high voltage semiconductor devices, e.g. such that transistors formed in the portion of the substrate located within the tub-like structure have a breakdown voltage exceeding 70V, even more particularly exceeding 100V.

Inventors

• LIU ZHIXIN
• LIAN YANJIE
• FU DAPING

Assignees

• 成都芯源系统有限公司

Dates

Publication Date

20260508

Application Date

20251105

Priority Date

20241105

Claims (20)

1. 1. A semiconductor device, comprising: a substrate including an initial substrate layer of a first conductivity type and an epitaxial layer of the first conductivity type formed on the initial substrate layer, and A barrel-like structure of a second conductivity type formed in the substrate, wherein the second conductivity type is opposite to the first conductivity type, wherein The tub-like structure has a bottom layer of a second conductivity type buried in the initial substrate layer, and a peak doping concentration plane of the bottom layer has a predetermined buried depth from a top surface of the initial substrate layer, the predetermined buried depth being substantially greater than 0.5 μm.
2. 2. The semiconductor device of claim 1, wherein the bottom layer is doped with phosphorus.
3. 3. The semiconductor device of claim 1, wherein said bottom layer is doped with a dopant of a second conductivity type suitable and compatible with high energy implantation processes.
4. 4. The semiconductor device of claim 1, wherein the bottom layer has a bottom layer doping concentration that is lower than a doping concentration of a buried region or buried layer formed in the initial substrate layer by a low energy implantation process.
5. 5. The semiconductor device of claim 1, wherein the bottom layer has a bottom layer doping concentration that is 1e 1cm -3 to 1e3 cm -3 lower than a doping concentration of a buried region or buried layer formed in the initial substrate layer by a low energy implantation process.
6. 6. The semiconductor device of claim 1, wherein the tub-like structure further comprises a plurality of sidewalls in contact with or connected to the bottom layer, and each of the plurality of sidewalls extends from a top surface of the substrate down into the substrate until at least in contact with or connected to the bottom layer.
7. 7. The semiconductor device of claim 6, wherein the plurality of sidewalls form a closed loop and define a top plan shape of the tub-like structure when viewed from a top plan view, and the top plan shape of the tub-like structure is rectangular, or quadrilateral, or polygonal, or circular.
8. 8. The semiconductor device of claim 6, wherein each of the plurality of sidewalls includes a buried connection region in contact with at least the bottom layer.
9. 9. The semiconductor device of claim 8, wherein the buried connection region of each of the plurality of sidewalls is a first buried layer formed in the initial substrate layer and the bottom layer is a second buried layer formed in the initial substrate layer having a greater buried depth in the substrate than the buried connection region.
10. 10. The semiconductor device of claim 8, wherein the buried connection region is doped with antimony or arsenic.
11. 11. The semiconductor device of claim 8, wherein said buried connection region is doped with a dopant of a second conductivity type suitable and compatible with a low energy implantation process.
12. 12. The semiconductor device of claim 1, further comprising: a transistor formed in a portion of the substrate within the tub-like structure.
13. 13. The semiconductor device of claim 12, wherein the transistor comprises a plurality of transistor cells, and each of the plurality of transistor cells comprises: A source region of a second conductivity type formed in the substrate and located near a top surface of the substrate; a drain region of a second conductivity type formed in the substrate and located near a top surface of the substrate, the drain region being separated from the source region; a body region of the first conductivity type disposed around the source region; a body contact region of the first conductivity type formed immediately adjacent to the source region; a drift region of a second conductivity type formed in the substrate, surrounding the drain region and separated from the source region, and And a gate region formed between the source region and the drain region and near one side of the source region.
14. 14. The semiconductor device of claim 13 wherein each of the plurality of transistor cells further comprises a body well region of a first conductivity type formed in the substrate around the body region.
15. 15. The semiconductor device of claim 13 or 14, wherein the transistor has a vertical junction breakdown voltage between the body region and the bottom layer that increases with an increase in a vertical junction breakdown control distance, the vertical junction breakdown control distance being substantially the vertical distance between a bottom surface of the drift region and a peak doping concentration plane of the bottom layer.
16. 16. The semiconductor device of claim 13, wherein each of the plurality of transistor cells further comprises: a RESURF region of the first conductivity type formed around and below the body region and the drift region and surrounding the body region and the drift region.
17. 17. The semiconductor device of claim 16, wherein the transistor has a vertical junction breakdown voltage between the body region and the bottom layer that increases with an increase in a vertical junction breakdown control distance, the vertical junction breakdown control distance being substantially the vertical distance between a bottom surface of the RESURF region to a peak doping concentration plane of the bottom layer.
18. 18. The semiconductor device according to claim 12, wherein the transistor has a breakdown voltage of not less than 70V.
19. 19. The semiconductor device according to claim 12, wherein the transistor has a breakdown voltage of not less than 100V.
20. 20. The semiconductor device of claim 1, wherein a thickness of the epitaxial layer is in a range of 8 μm to 16 μm.

Description

Semiconductor device and method for manufacturing the same Technical Field Embodiments of the present application relate generally to semiconductor devices and, more particularly, but not exclusively, to high voltage semiconductor devices and methods of manufacturing the same. Background Power transistors, such as high voltage Metal-Qxide Semiconductor (MOS) transistors, are widely used in a variety of power management scenarios, including power switching elements for use as power management devices in industrial and/or consumer electronic devices. In most high-current or high-power application fields such as notebook computers, servers, automobiles, and the like, transistors with high voltage resistance are required. Disclosure of Invention According to an embodiment of the present invention, there is provided a semiconductor device having a substrate of a first conductivity type, and a barrel-like structure of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. In one embodiment, the substrate includes an initial substrate layer of a first conductivity type, and an epitaxial layer of the first conductivity type formed on the initial substrate layer. In one embodiment, the tub-like structure includes a bottom layer of a second conductivity type embedded in the initial substrate layer. In one embodiment, the bottom layer has a peak doping concentration plane having a predetermined buried depth of substantially greater than 0.5 μm from the top surface of the initial substrate layer. In one embodiment, the tub-like structure further comprises a plurality of sidewalls in contact with or connected to the bottom layer, each of the plurality of sidewalls extending from the substrate top surface down to at least in contact with or connected to the bottom layer. In one embodiment, the semiconductor device further includes a transistor formed in a portion of the substrate that is located within the tub-like structure. In one embodiment, the transistor has a breakdown voltage of more than 70V, even more particularly up to more than 100V. According to one embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device has a substrate of a first conductivity type, and a tub-like structure of a second conductivity type formed in the substrate, the second conductivity type being opposite to the first conductivity type. In one embodiment, the tub-like structure comprises a bottom layer and a plurality of sidewalls in contact with the bottom layer, and each of the plurality of sidewalls comprises a buried connection region, i.e. a first buried layer, the bottom layer comprising a second buried layer having a buried depth in the substrate that is greater than a buried depth of the buried connection region in the substrate when measured with reference to a top surface of the substrate. In one embodiment, the semiconductor device further includes a transistor formed within the tub-like structure. In one embodiment, the transistor has a breakdown voltage of more than 70V, even more particularly up to more than 100V. According to an embodiment of the present disclosure, there is also provided a method of manufacturing a semiconductor device. The method includes forming a substrate of a first conductivity type that includes a bottom layer of the tub-like structure. The bottom layer being of a second conductivity type opposite the first conductivity type and having a peak doping concentration plane having a predetermined bottom layer buried depth of substantially greater than 0.5 μm from a top surface of an initial substrate layer of the substrate. In one embodiment, the step of forming the substrate further comprises forming a buried connection region in the substrate for each of the plurality of sidewalls of the tub-like structure, and the buried connection region is in contact with at least the bottom layer. The buried depth of the bottom layer in the substrate is greater than the buried depth of the buried connection region in the substrate. In one embodiment, forming the substrate further comprises forming an epitaxial layer having a thickness in the range of 8 μm to 16 μm on the initial substrate layer. In one embodiment, the method further comprises forming a drift region of the second conductivity type for each of a plurality of transistor cells of a high voltage transistor to be fabricated in the substrate. In one embodiment, the method may optionally further comprise forming RESURF regions of the first conductivity type in the epitaxial layer for each of the plurality of transistor cells of the high voltage transistor. In one embodiment, the method may optionally further comprise forming a sidewall connection region of the second conductivity type in the epitaxial layer for each of the plurality of sidewalls of the tub-like structure. The sidewall connection region may be a buried doped region buried in the epi