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CN-122002853-A - Transistor and method for manufacturing the same

CN122002853ACN 122002853 ACN122002853 ACN 122002853ACN-122002853-A

Abstract

The present disclosure provides a transistor and a method of manufacturing the same, which belongs to the technical field of semiconductors. The transistor comprises a substrate, a heterojunction, an electrode assembly and a cap layer, wherein the heterojunction comprises a channel layer and a barrier layer which are sequentially laminated on the substrate, the electrode assembly comprises a source electrode, a drain electrode and a grid electrode, the source electrode and the drain electrode are positioned on two sides of the grid electrode and are respectively and electrically connected with the heterojunction, the cap layer is positioned on one side of the barrier layer away from the substrate and on one side of the drain electrode, which is close to the grid electrode, and the cap layer is in contact with the drain electrode and is arranged at intervals with the grid electrode. The transistor has smaller on-resistance and better voltage resistance.

Inventors

  • Chen Kuangli
  • WANG RUI
  • YANG TING
  • YANG YING
  • WANG JIANGBO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251219

Claims (10)

  1. 1. A transistor is characterized by comprising a substrate (10), a heterojunction, an electrode assembly and a cap layer (40), The heterojunction comprises a channel layer (20) and a barrier layer (30) which are sequentially laminated on the substrate (10); The electrode assembly comprises a source electrode (51), a drain electrode (52) and a grid electrode (53), wherein the source electrode and the drain electrode (52) are positioned on two sides of the grid electrode (53), and the source electrode (51), the drain electrode (52) and the grid electrode (53) are respectively and electrically connected with the heterojunction; The cap layer (40) is located on a side of the barrier layer (30) remote from the substrate (10) and on a side of the drain (52) adjacent to the gate (53), the cap layer (40) being in contact with the drain (52) and spaced apart from the gate (53).
  2. 2. The transistor according to claim 1, wherein the cap layer (40) is a monolithic structure extending from one side to the other side of the barrier layer (30) in a direction perpendicular to an arrangement direction of the source electrode (51) and the drain electrode (52).
  3. 3. A transistor according to claim 2, characterized in that the entire surface of the cap layer (40) adjacent to the substrate (10) is connected to the barrier layer (30), or The transistor further comprises a spacer dielectric layer (64), the spacer dielectric layer (64) comprises a plurality of dielectric blocks (641) which are arranged at intervals along a first direction, the first direction is intersected with the arrangement direction of the source electrode (51) and the drain electrode (52), one part of the cap layer (40) is located between the plurality of dielectric blocks (641) and connected with the barrier layer (30), and the other part of the cap layer (40) is located on the surface, away from the substrate (10), of the plurality of dielectric blocks (641).
  4. 4. A transistor according to claim 1, characterized in that the cap layer (40) comprises a plurality of block structures (41) arranged at intervals, each block structure (41) being in contact with the drain electrode (52).
  5. 5. A transistor according to claim 4, characterized in that the width a of the orthographic projection of each block structure (41) on the barrier layer (30) is 0.5 μm-3 μm, and the spacing h between two adjacent block structures (41) is 0.5 μm-3 μm.
  6. 6. A transistor according to any of claims 1 to 5, characterized in that the length L of the orthographic projection of the cap layer (40) on the barrier layer (30) is 2 μm-15 μm.
  7. 7. A transistor according to any of claims 1 to 5, characterized in that the cap layer (40) is a GaN layer, scAlN layer, inGaN layer or AlGaN layer.
  8. 8. The transistor according to any of claims 1 to 5, wherein the barrier layer (30) comprises a first barrier layer (31) and a second barrier layer (32) stacked in sequence on the channel layer (20), the transistor further comprising a first dielectric layer (61), the first dielectric layer (61) being located between the first barrier layer (31) and the second barrier layer (32); The gate (53) penetrates the second barrier layer (32) and is connected to the first dielectric layer (61).
  9. 9. The transistor according to claim 8, characterized in that the distance D between the orthographic projection of the contact surface of the gate (53) with the first dielectric layer (61) on the substrate (10) and the orthographic projection of the contact surface of the drain (52) with the first barrier layer (31) on the substrate (10) is 10 μm-22 μm.
  10. 10. A method of manufacturing a transistor, comprising: Forming a heterojunction and a cap layer on a substrate in sequence, wherein the heterojunction comprises a channel layer and a barrier layer which are sequentially laminated on the substrate, and the cap layer is positioned on one side of the barrier layer away from the substrate; preparing an electrode assembly, wherein the electrode assembly comprises a source electrode, a grid electrode and a drain electrode, the source electrode and the drain electrode are positioned on two sides of the grid electrode, and the source electrode, the drain electrode and the grid electrode are respectively and electrically connected with the heterojunction; Wherein the cap layer is positioned on one side of the drain electrode, which is close to the gate electrode, and the cap layer is in contact with the drain electrode and is arranged at intervals with the gate electrode.

Description

Transistor and method for manufacturing the same Technical Field The disclosure relates to a transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. Background Transistors are a common semiconductor device and are widely used in various electronic devices. In the related art, a transistor includes a substrate, a channel layer, a barrier layer, and an electrode assembly. Wherein the channel layer and the barrier layer are sequentially laminated on the substrate. The electrode assembly includes a source electrode, a drain electrode, and a gate electrode. The source electrode and the drain electrode are positioned on two sides of the grid electrode, and the grid electrode, the source electrode and the drain electrode are respectively connected with the barrier layer. The voltage withstand performance of a transistor is positively correlated with the length of the drift region, i.e., the greater the length of the drift region, the better the voltage withstand performance of the transistor, but the greater the on-resistance of the transistor. The voltage withstand performance and on-resistance requirements of transistors conflict at the device physical level. Disclosure of Invention The embodiment of the disclosure provides a transistor and a manufacturing method thereof, which can improve the voltage resistance of the transistor under the condition of smaller on-resistance of the transistor. The technical scheme is as follows: The embodiment of the disclosure provides a transistor, which comprises a substrate, a heterojunction, an electrode assembly and a cap layer, wherein the heterojunction comprises a channel layer and a barrier layer which are sequentially stacked on the substrate, the electrode assembly comprises a source electrode, a drain electrode and a grid electrode, the source electrode and the drain electrode are positioned on two sides of the grid electrode and are respectively and electrically connected with the heterojunction, the cap layer is positioned on one side, far away from the substrate, of the barrier layer and on one side, close to the grid electrode, of the drain electrode, and the cap layer is in contact with the drain electrode and is arranged at intervals with the grid electrode. In one possible embodiment, the cap layer is a monolithic structure extending from one side to the other side of the barrier layer in a direction perpendicular to the direction of alignment of the source and drain electrodes. The transistor also comprises a spacing dielectric layer, wherein the spacing dielectric layer comprises a plurality of dielectric blocks which are arranged at intervals along a first direction, the first direction is intersected with the arrangement direction of the source electrode and the drain electrode, one part of the cap layer is positioned between the plurality of dielectric blocks and connected with the barrier layer, and the other part of the cap layer is positioned on the surface, away from the substrate, of the plurality of dielectric blocks. In another possible embodiment, the cap layer includes a plurality of block structures arranged at intervals, each of the block structures being in contact with the drain electrode. Optionally, the length of the orthographic projection of the cap layer on the barrier layer is 2 μm-15 μm. Optionally, the width of orthographic projection of each block structure on the barrier layer is 0.5 μm-3 μm, and the interval between two adjacent block structures is 0.5 μm-3 μm. Optionally, the cap layer is a GaN layer, scAlN layer, inGaN layer, or AlGaN layer. Optionally, the barrier layer comprises a first barrier layer and a second barrier layer which are sequentially laminated on the channel layer, the transistor further comprises a first dielectric layer, the first dielectric layer is positioned between the first barrier layer and the second barrier layer, and the grid penetrates through the second barrier layer and is connected with the first dielectric layer. Optionally, a distance between an orthographic projection of a contact surface of the gate electrode and the first dielectric layer on the substrate and an orthographic projection of a contact surface of the drain electrode and the first barrier layer on the substrate is 10 μm-22 μm. The embodiment of the disclosure also provides a manufacturing method of the transistor. The manufacturing method comprises the steps of sequentially forming a heterojunction and a cap layer on a substrate, wherein the heterojunction comprises a channel layer and a barrier layer which are sequentially stacked on the substrate, the cap layer is located on one side, away from the substrate, of the barrier layer, an electrode assembly is prepared, the electrode assembly comprises a source electrode, a grid electrode and a drain electrode, the source electrode and the drain electrode are located on two sides of the grid electrode, the source electrode, the drain elect