CN-122002856-A - Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof

Abstract

The invention provides a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method thereof, wherein the manufacturing method of the silicon carbide metal oxide semiconductor field effect transistor comprises the following steps of providing a silicon carbide substrate; forming an N-type silicon carbide epitaxial layer on a silicon carbide substrate, wherein the N-type silicon carbide epitaxial layer comprises a top surface, forming two doped structures in the N-type silicon carbide epitaxial layer and adjacent to the top surface, wherein each doped structure comprises a P-type well, an N-type doped region and a P-type doped region, the N-type doped region is positioned in the P-type well, the P-type doped region is positioned in the P-type well and adjacent to the N-type doped region, depositing a silicon-rich nitride film on the top surface, depositing a gate oxide layer on the silicon-rich nitride film, isolating the gate oxide layer from the silicon carbide substrate through the silicon-rich nitride film, performing a post-oxidation annealing process on the gate oxide layer, and forming a gate structure on the gate oxide layer.

Inventors

• WANG PEIREN
• HUANG PINYAN

Assignees

• 积亚半导体股份有限公司

Dates

Publication Date

20260508

Application Date

20241231

Priority Date

20241108

Claims (10)

1. 1. A method of fabricating a silicon carbide metal oxide semiconductor field effect transistor, comprising the steps of: providing a silicon carbide substrate; Forming an N-type silicon carbide epitaxial layer on the silicon carbide substrate, wherein the N-type silicon carbide epitaxial layer comprises a top surface; forming two doped structures in the N-type silicon carbide epitaxial layer and adjacent to the top surface, wherein each doped structure comprises a P-type well, an N-type doped region and a P-type doped region, the N-type doped region is positioned in the P-type well, and the P-type doped region is positioned in the P-type well and adjacent to the N-type doped region; depositing a silicon-rich nitride film on the top surface; Depositing a gate oxide layer on the silicon-rich nitride film, wherein the gate oxide layer and the N-type silicon carbide epitaxial layer are isolated by the silicon-rich nitride film; Performing a post oxidation annealing process on the gate oxide layer, and Forming a gate structure on the gate oxide layer.
2. 2. The method of claim 1, wherein the silicon-rich nitride film has a thickness between To the point of Between them.
3. 3. The method of claim 1, wherein the silicon-rich nitride film is deposited on the top surface by an atomic layer deposition process.
4. 4. The method of claim 1, wherein the post oxidation annealing process is a high temperature anneal performed in a nitrogen monoxide or nitrous oxide ambient.
5. 5. The method of claim 1, wherein the gate structure is made of polysilicon or metal.
6. 6. A silicon carbide metal oxide semiconductor field effect transistor comprising: A silicon carbide substrate; an N-type silicon carbide epitaxial layer formed on the silicon carbide substrate and comprising a top surface; The two doped structures are formed in the N-type silicon carbide epitaxial layer and adjacent to the top surface, wherein each doped structure comprises a P-type well, an N-type doped region and a P-type doped region, the N-type doped region is positioned in the P-type well, and the P-type doped region is positioned in the P-type well and adjacent to the N-type doped region; A silicon-rich nitride film on the top surface; A gate oxide layer on the silicon-rich nitride film, wherein the gate oxide layer and the N-type silicon carbide epitaxial layer are isolated by the silicon-rich nitride film, and And a gate structure on the gate oxide layer.
7. 7. The silicon carbide MOSFET of claim 6 wherein the silicon-rich nitride film has a thickness between To the point of Between them.
8. 8. The silicon carbide mosfet of claim 6, wherein said silicon-rich nitride film is deposited on said top surface by an atomic layer deposition process.
9. 9. The silicon carbide mosfet of claim 6, wherein said gate oxide layer is treated by performing a post-oxidation anneal process, said post-oxidation anneal process being a high temperature anneal performed in a nitric oxide or nitrous oxide ambient.
10. 10. The silicon carbide mosfet of claim 6, wherein the gate structure is made of polysilicon or metal.

Description

Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof Technical Field The present invention relates to a silicon carbide mosfet and a method for fabricating the same, and more particularly, to a silicon carbide mosfet with improved interface quality for improved channel mobility and a method for fabricating the same. Background The silicon carbide metal oxide semiconductor field effect Transistor (Silicon Carbide Metal Oxide Semiconductor FIELD EFFECT Transistor, siC MOSFET for short) has the characteristics of high temperature resistance, high voltage resistance, low on resistance and the like, is suitable for being applied to high-speed power elements, and can provide higher electron mobility and switching speed. However, the interface between the silicon carbide substrate and the gate oxide layer of the silicon carbide mosfet is prone to generate oxygen vacancy defects to increase the interface defect density (INTERFACE TRAP DENSITY), so that electrons will be trapped when flowing through the interface to reduce the channel mobility and increase the channel resistance (CHANNEL RESISTANCE). Since the channel resistance occupies a larger proportion of the on resistance, the increase of the channel resistance also increases the on resistance, which causes the power loss of the element to become larger and causes serious reliability problems. Therefore, how to design a silicon carbide mosfet and a method for manufacturing the same, which can improve the above problems, is a considerable research problem. Disclosure of Invention The invention aims to provide a manufacturing method of a silicon carbide metal oxide semiconductor field effect transistor for improving interface quality and channel mobility. The manufacturing method of the silicon carbide metal oxide semiconductor field effect transistor comprises the steps of providing a silicon carbide substrate, forming an N-type silicon carbide epitaxial layer on the silicon carbide substrate, forming two doped structures in the N-type silicon carbide epitaxial layer and adjacent to the top surface, wherein each doped structure comprises a P-type well, an N-type doped region and a P-type doped region, the N-type doped region is located in the P-type well, the P-type doped region is located in the P-type well and adjacent to the N-type doped region, depositing a silicon-rich nitride film on the top surface, depositing a gate oxide layer on the silicon-rich nitride film, isolating the gate oxide layer and the N-type silicon carbide epitaxial layer through the silicon-rich nitride film, performing a post oxidation annealing process on the gate oxide layer, and forming a gate structure on the gate oxide layer. In one embodiment of the present invention, the thickness of the silicon-rich nitride film is betweenTo the point ofBetween them. In one embodiment of the present invention, the silicon-rich nitride film is deposited on the top surface by an atomic layer deposition process. In one embodiment of the present invention, the post-oxidation annealing process is a high temperature anneal performed in a nitric oxide or nitrous oxide ambient. In one embodiment of the present invention, the gate structure is made of polysilicon or metal. The invention also provides a silicon carbide metal oxide semiconductor field effect transistor. The silicon carbide metal oxide semiconductor field effect transistor comprises a silicon carbide substrate, an N-type silicon carbide epitaxial layer, two doped structures, a silicon-rich nitride film, a gate oxide layer and a gate structure. The N-type silicon carbide epitaxial layer comprises a top surface, two doped structures are formed in the N-type silicon carbide epitaxial layer and adjacent to the top surface, each doped structure comprises a P-type well, an N-type doped region and a P-type doped region, the N-type doped region is located in the P-type well, the P-type doped region is located in the P-type well and adjacent to the N-type doped region, the silicon-rich nitride film is located on the top surface, the grid oxide layer is located on the silicon-rich nitride film, the grid oxide layer and the N-type silicon carbide epitaxial layer are isolated through the silicon-rich nitride film, and the grid structure is located on the grid oxide layer. Drawings Fig. 1 is a schematic structural diagram of a silicon carbide mosfet according to the present invention. Fig. 2 is a flow chart of a method of fabricating a silicon carbide mosfet according to the present invention. Description of the reference numerals 1. Silicon carbide metal oxide semiconductor field effect transistor 10. Silicon carbide substrate 20 N-type silicon carbide epitaxial layer 21. Top surface 30. Doping structure 31 P-type well 32 N-type doped region 33 P-type doped region 40. Silicon-rich nitride film 50. Gate oxide layer 60. Gate structure S1-S7. Detailed Description Since the various aspects and embodiments are