CN-122002857-A - LDMOS (laterally diffused metal oxide semiconductor) and forming method thereof

Abstract

The LDMOS and the forming method thereof comprise a substrate, a body region, a grid structure, a first doped region and an external doped region, wherein the body region is positioned in the substrate, part of the grid structure is positioned right above the body region, the first doped region is positioned in the body region at one side of the grid structure, the doping type of the first doped region is different from that of the body region, the external doped region is positioned in the body region at one side, far away from the grid structure, of the first doped region, the external doped region extends along the extending direction of the grid structure, and the doping type of the external doped region is the same as that of the body region. The external doped region extends along the extending direction of the grid structure, so that the occurrence of the phenomenon of doped ion mutual dissolution can be effectively reduced, and the effective channel width can be effectively increased to reduce the starting resistance.

Inventors

• YAN WENQING
• TAO DONGYAN
• LIU JINHUA

Assignees

• 中芯北方集成电路制造(北京)有限公司
• 中芯国际集成电路制造(上海)有限公司

Dates

Publication Date

20260508

Application Date

20241108

Claims (18)

1. 1. An LDMOS, comprising: A substrate; a body region located within the substrate; A gate structure, a portion of which is located directly above the body region; The first doped region is positioned in the body region at one side of the grid structure, and the doping type of the first doped region is different from that of the body region; The external doped region is positioned in the body region at one side of the first doped region far away from the gate structure, the external doped region extends along the extending direction of the gate structure, and the doping type of the external doped region is the same as that of the body region.
2. 2. The LDMOS of claim 1 wherein the externally doped region has a trapezoidal, diamond or triangular shape in a plane parallel to the substrate surface.
3. 3. The LDMOS of claim 1 wherein at most only one of the two ends of the external doped region in the direction of extension of the gate structure is in contact with the gate structure.
4. 4. The LDMOS of claim 1 wherein a surface of the external doped region is lower than a surface of the first doped region in a direction perpendicular to the surface of the substrate.
5. 5. The LDMOS of claim 4 wherein a surface of the external doped region is lower than a bottom surface of the first doped region in a direction perpendicular to the surface of the substrate.
6. 6. The LDMOS of claim 4 wherein the surface of the external doped region is 40nm to 70nm lower than the surface of the first doped region in a direction perpendicular to the surface of the substrate.
7. 7. The LDMOS of any of claims 4 through 6 wherein the external doped region is rectangular in a plane parallel to the substrate surface.
8. 8. The LDMOS of claim 1 wherein the LDMOS has 2 of the gate structures and 2 of the first doped regions; The 2 grid structures are respectively positioned on the substrates at the two sides of the body region; the 2 first doped regions are respectively positioned in the body regions at two sides of the external doped region.
9. 9. The LDMOS as recited in claim 8, wherein the width of the external doped region is greater than a design rule.
10. 10. The LDMOS of claim 9 wherein the width of the external doped region is greater than 0.26 μm.
11. 11. The LDMOS of claim 1, wherein the gate structure comprises: The grid electrode lamination comprises a grid electrode and a grid dielectric layer, and the grid dielectric layer is positioned between the grid electrode and the substrate; and the side wall is positioned on the side wall of the grid electrode lamination.
12. 12. The LDMOS of claim 1, further comprising: The contact plug is electrically connected with the external doped region and the first doped region; And the connecting layer is positioned between the contact plug and the external doped region and extends to the first doped region.
13. 13. The LDMOS of claim 1, further comprising: The drift region is positioned in the substrate at one side of the body region, and the doping type of the drift region is the same as that of the first doping region; The gate structure spans from above the drift region to above the body region; The second doped region is positioned in the drift region far away from one side of the body region, is separated from the grid structure along the direction of the connecting line of the drift region and the body region, and has the same doping type as the first doped region.
14. 14. The LDMOS of claim 1 wherein the body region is a P-type doped region.
15. 15. The method for forming the LDMOS is characterized by comprising the following steps of: Providing a substrate; Forming a body region within the substrate; forming a gate structure on the substrate, wherein part of the gate structure is positioned right above the body region; forming a first doped region in a body region at one side of the gate structure, wherein the doping type of the first doped region is different from that of the body region; and forming an external doped region in the body region at one side of the first doped region far away from the gate structure, wherein the external doped region extends along the extending direction of the gate structure, and the doping type of the external doped region is the same as that of the body region.
16. 16. The method of forming of claim 15, wherein forming an external doped region in the body region on a side of the first doped region remote from the gate structure comprises: Forming a recess in the body region; And forming the external doped region at the bottom of the groove.
17. 17. The method of forming of claim 16, wherein forming a gate structure on the substrate comprises: Forming a gate stack on the substrate, wherein the gate stack comprises a gate electrode and a gate dielectric layer, and the gate dielectric layer is positioned between the gate electrode and the substrate; Forming a side wall on the side wall of the grid electrode lamination; after forming the side wall, forming a groove in the body region; After the groove is formed, a first doped region is formed in the body region at one side of the grid structure; and after the first doped region is formed, forming the external doped region at the bottom of the groove.
18. 18. The method of forming as in claim 15, further comprising: Forming a drift region in the substrate, wherein the drift region is positioned on one side of the body region, and the doping type of the drift region is the same as that of the first doping region; Forming a gate structure from above the drift region to above the body region; In the step of forming a first doped region in the body region at one side of the gate structure, a first doped region in the body region at one side of the gate structure and a second doped region in the drift region at one side away from the body region are formed.

Description

LDMOS (laterally diffused metal oxide semiconductor) and forming method thereof Technical Field The present disclosure relates to semiconductor structures, and more particularly, to an LDMOS and a method for forming the same. Background The power semiconductor device plays an important role in the fields of power integrated circuits and high-voltage integrated circuits, and is widely applied to various fields such as power management, automotive electronics, display driving, industrial electronics and the like. The LDMOS is a key component of a power integrated circuit by virtue of the characteristic that coplanar electrodes of the LDMOS are easy to integrate. The LDMOS is mainly of two types, namely a vertical double-diffused MOS (VDMOS) and a lateral double-diffused MOS (LDMOS). Among them, LDMOS are widely adopted in the industry because they are more easily compatible with complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) processes. In the practical application of LDMOS, the equipotential of the active region and the body region is often the same. LDMOS therefore often will dock the source and body regions together and out together. The LDMOS led out by the existing source region and the body region together often has the problem of poor performance. Disclosure of Invention The invention solves the problem of improving the performance of the LDMOS led out by the source region and the body region together. In order to solve the above problems, the present invention provides an LDMOS, comprising: The semiconductor device comprises a substrate, a body region, a grid structure, a first doped region, an external doped region, a first doped region, a second doped region and a second doped region, wherein the body region is positioned in the substrate, part of the grid structure is positioned right above the body region, the first doped region is positioned in the body region at one side of the grid structure, the doping type of the first doped region is different from that of the body region, the external doped region is positioned in the body region at one side, far away from the grid structure, of the first doped region, the external doped region extends along the extending direction of the grid structure, and the doping type of the external doped region is the same as that of the body region. Optionally, in a plane parallel to the surface of the substrate, the external doped region is trapezoidal, rhombic or triangular. Optionally, only one of the two ends of the external doped region along the extending direction of the gate structure is in contact with the gate structure at most. Optionally, in a direction perpendicular to the surface of the substrate, the surface of the external doped region is lower than the surface of the first doped region. Optionally, in a direction perpendicular to the surface of the substrate, the surface of the external doped region is lower than the bottom surface of the first doped region. Optionally, in a direction perpendicular to the surface of the substrate, the surface of the external doped region is 40nm to 70nm lower than the surface of the first doped region. Optionally, in a plane parallel to the surface of the substrate, the external doped region is rectangular. Optionally, the LDMOS is provided with 2 gate structures and 2 first doped regions, the 2 gate structures are respectively positioned on the substrates at two sides of the body region, and the 2 first doped regions are respectively positioned in the body regions at two sides of the external doped region. Optionally, the width of the external doped region is larger than the design rule. Optionally, the width of the external doped region is greater than 0.26 μm. Optionally, the gate structure comprises a gate stack, a side wall and a side wall, wherein the gate stack comprises a gate electrode and a gate dielectric layer, the gate dielectric layer is positioned between the gate electrode and the substrate, and the side wall is positioned on the side wall of the gate stack. Optionally, the semiconductor device further comprises a contact plug electrically connected with the external doped region and the first doped region, and a connection layer positioned between the contact plug and the external doped region and extending to the first doped region. Optionally, the semiconductor device further comprises a drift region, a second doped region and a first doped region, wherein the drift region is positioned in the substrate at one side of the body region, the doping type of the drift region is the same as that of the first doped region, the gate structure spans from the drift region to the body region, the second doped region is positioned in the drift region at one side far away from the body region, the second doped region is separated from the gate structure along the direction of the connection line of the drift region and the body region, and the doping types of the second