CN-122002859-A - Semiconductor device, manufacturing method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, a first region, a well region, a second region, a grid and at least one third region, wherein the first surface and the second surface are oppositely arranged, the semiconductor body further comprises a first region, the well region and at least one second region, the first region is of a first conductivity type and is located on the first surface, the well region is of a second conductivity type and is located on one side, away from the first surface, of the first region, the second region is of the first conductivity type and is located on one side, away from the first surface, at least one third region group is arranged in the second region, each third region group comprises at least one third region, the third region is of the second conductivity type, a fourth region is arranged in the third region, the fourth region is of the first conductivity type, and the grid is located in the grid groove. The invention can solve the problem that the reliability of the semiconductor device is reduced due to the too high electric field at the bottom and the corners of the grid electrode groove.

Inventors

• LI KUN
• DING XIAO
• LI FEIFEI

Assignees

• 长飞先进半导体(武汉)有限公司

Dates

Publication Date

20260508

Application Date

20260204

Claims (14)

1. 1. A semiconductor device, the semiconductor device comprising: The semiconductor comprises a semiconductor body, a first surface, a second surface, a first region, a well region, at least one third region, a fourth region, at least one gate trench, at least one first region and at least one second region, wherein the first region is of a first conductivity type and is positioned on the first surface, the well region is of a second conductivity type and is positioned on one side, far away from the first surface, of the first region, the second region is of the first conductivity type and is positioned on one side, far away from the first surface, of the well region, the first surface is further provided with at least one gate trench, the gate trench penetrates through the well region, at least one third region group is arranged in the second region, each third region group comprises at least one third region, the third region is of the second conductivity type, the ion doping concentration of the third region is larger than that of the well region, and the fourth region is arranged in the third region and is of the first conductivity type; the grid electrode is positioned in the grid electrode groove; A source electrode positioned on the first surface; and the drain electrode is positioned on the second surface.
2. 2. The semiconductor device according to claim 1, wherein the third region group includes at least two of the third regions arranged in a thickness direction of the semiconductor device; In two adjacent third areas of the same third area group, the orthographic projection area of the third area close to the first surface on the second surface is smaller than the orthographic projection area of the third area far away from the first surface on the second surface; and the orthographic projection of the third area on the second surface, which is close to the first surface, is covered by the orthographic projection of the third area on the second surface, which is far from the first surface.
3. 3. The semiconductor device according to claim 2, wherein, The ion doping concentration of the third region far from the first surface is smaller than that of the third region close to the first surface in the same third region group, the ion doping concentration of the fourth region far from the first surface in the same third region group is smaller than that of the fourth region close to the first surface, and/or the orthographic projection of the fourth region in the third region far from the first surface in the adjacent two third regions in the same third region group on the second surface coincides with the orthographic projection of the third region close to the first surface.
4. 4. The semiconductor device of claim 1, wherein the semiconductor body comprises at least two of the second regions aligned in a thickness direction of the semiconductor device, and wherein the second regions remote from the first surface have a lower ion doping concentration than the second regions proximate to the first surface; the third region groups in two adjacent second regions are in one-to-one correspondence and contact arrangement.
5. 5. The semiconductor device of claim 1, further comprising a first insulating layer disposed on an inner wall of the gate trench for isolating the gate from the semiconductor body, wherein the third set of regions is disposed at least in part at a bottom wall of the first insulating layer, wherein the third set of regions is in contact with a bottom wall of the first insulating layer.
6. 6. The semiconductor device of claim 1, further comprising a fifth region between the well region and the at least one second region, the fifth region being disposed of the first conductivity type, the fifth region having a greater ion doping concentration than the second region, the gate trench extending through the fifth region.
7. 7. The semiconductor device of claim 1, further comprising a sixth region disposed of the second conductivity type and at the first surface, the sixth region extending through the first region and contacting the well region.
8. 8. The semiconductor device of claim 7, wherein the sixth region further extends through the well region and contacts the third region of the third region group.
9. 9. A method of manufacturing a semiconductor device, the method comprising: The method comprises the steps of providing a semiconductor body, wherein the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a first region, a well region and at least one second region, the first region is of a first conductivity type and is positioned on the first surface, the well region is of a second conductivity type and is positioned on one side of the first region away from the first surface, the second region is of the first conductivity type and is positioned on one side of the well region away from the first surface, the first surface is further provided with at least one gate groove penetrating through the well region, at least one third region group is arranged in the second region, each third region group comprises at least one third region, the third region is of the second conductivity type, the ion doping concentration of the third region is larger than that of the well region, and a fourth region is arranged in the third region and is of the first conductivity type; Forming a gate in the gate trench; forming a source electrode on the first surface of the semiconductor body; A drain is formed at the second surface of the semiconductor body.
10. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the providing a semiconductor body comprises: Providing a substrate; forming a first epitaxial layer on the substrate; forming the third set of regions within the first epitaxial layer; Forming a second epitaxial layer on the first epitaxial layer; The well region, the first region, and the gate trench are formed within the second epitaxial layer.
11. 11. The method for manufacturing a semiconductor device according to claim 9, wherein the third region group includes at least two of the third regions arranged in a thickness direction of the semiconductor device The forming the third set of regions within the first epitaxial layer includes: The third region away from the first surface, the fourth region located within the third region, and the third region close to the first surface are sequentially formed.
12. 12. A power module comprising a substrate and at least one semiconductor device according to any of claims 1-8, said substrate being arranged to carry said semiconductor device.
13. 13. A power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprising a circuit board and at least one semiconductor device according to any one of claims 1-8, the semiconductor device being electrically connected to the circuit board.
14. 14. A vehicle comprising a load and the power conversion circuit according to claim 13, wherein the power conversion circuit is configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.

Description

Semiconductor device, manufacturing method thereof, power module, power conversion circuit and vehicle Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, a power module, a power conversion circuit, and a vehicle. Background Silicon carbide (SiC) and other wide bandgap semiconductor materials are widely used in the fields of power electronics, automobiles, aerospace and the like due to their excellent high temperature performance, chemical stability and electronic characteristics. The trench silicon carbide Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in the related art has the advantages of large current density, small cell spacing and the like. However, the high electric field at the trench bottom and corners results in a high electric field across the gate oxide, which is prone to breakdown. Disclosure of Invention The invention provides a semiconductor device, a preparation method thereof, a power module, a power conversion circuit and a vehicle, and aims to solve the problem that the reliability of the semiconductor device is reduced due to overhigh electric field at the bottom and corners of a grid groove. According to an aspect of the present invention, there is provided a semiconductor device including: The semiconductor comprises a semiconductor body, a first surface, a second surface, a first region, a well region, at least one third region, a fourth region, at least one gate trench, at least one first region and at least one second region, wherein the first region is of a first conductivity type and is positioned on the first surface, the well region is of a second conductivity type and is positioned on one side, far away from the first surface, of the first region, the second region is of the first conductivity type and is positioned on one side, far away from the first surface, of the well region, the first surface is further provided with at least one gate trench, the gate trench penetrates through the well region, at least one third region group is arranged in the second region, each third region group comprises at least one third region, the third region is of the second conductivity type, the ion doping concentration of the third region is larger than that of the well region, and the fourth region is arranged in the third region and is of the first conductivity type; the grid electrode is positioned in the grid electrode groove; A source electrode positioned on the first surface; and the drain electrode is positioned on the second surface. Optionally, the third region group includes at least two third regions arranged in a thickness direction of the semiconductor device; In two adjacent third areas of the same third area group, the orthographic projection area of the third area close to the first surface on the second surface is smaller than the orthographic projection area of the third area far away from the first surface on the second surface; and the orthographic projection of the third area on the second surface, which is close to the first surface, is covered by the orthographic projection of the third area on the second surface, which is far from the first surface. Optionally, the ion doping concentration of the third region far from the first surface is smaller than that of the third region close to the first surface in the same third region group, and the ion doping concentration of the fourth region far from the first surface is smaller than that of the fourth region close to the first surface in the same third region group, and/or the orthographic projection of the fourth region in the third region far from the first surface on the second surface in the adjacent two third regions in the same third region group coincides with the orthographic projection of the third region close to the first surface. Optionally, the semiconductor body comprises at least two second regions arranged along the thickness direction of the semiconductor device, and the ion doping concentration of the second regions far from the first surface is smaller than that of the second regions close to the first surface; the third region groups in two adjacent second regions are in one-to-one correspondence and contact arrangement. Optionally, the semiconductor device further comprises a first insulating layer, wherein the first insulating layer is arranged on the inner wall of the grid groove and used for isolating the grid from the semiconductor body, and the third region group is arranged at the bottom wall of at least part of the first insulating layer, wherein the third region group is in contact with the bottom wall of the first insulating layer. Optionally, the semiconductor device further includes a fifth region located between the well region and the at least one second region, the fifth region being set to the first conductivity type, an ion doping concent