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CN-122002860-A - Semiconductor device, manufacturing method thereof, power module, power conversion circuit and vehicle

CN122002860ACN 122002860 ACN122002860 ACN 122002860ACN-122002860-A

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, a grid insulating layer, a grid electrode layer, a first dielectric layer, a plurality of first contact holes and a second dielectric layer, wherein the first surface and the second surface are oppositely arranged, the first surface and the second surface are further arranged, the grid electrode insulating layer is located on the first surface, the grid electrode layer is located on one side, far away from the first surface, of the grid electrode layer, the first dielectric layer is located on one side, far away from the first surface, the first contact holes penetrate through the grid insulating layer, the grid electrode layer and the first dielectric layer and expose the side wall of the grid insulating layer, the side wall of the grid electrode layer and the side wall of the first dielectric layer, the second dielectric layer is located on the side wall of the first contact holes, the second dielectric layer located on the same first contact holes forms a second contact hole, and the second contact hole exposes at least part of the surface of the first region. The invention can solve the problem of larger contact hole position deviation.

Inventors

  • ZHENG LULU

Assignees

  • 安徽长飞先进半导体股份有限公司

Dates

Publication Date
20260508
Application Date
20260204

Claims (11)

  1. 1. A semiconductor device, the semiconductor device comprising: A semiconductor body including oppositely disposed first and second surfaces, the semiconductor body further including a first region disposed of a first conductivity type and located on the first surface, a well region disposed of a second conductivity type and located between the first and second regions, and a second region disposed of the first conductivity type; a gate insulating layer located on the first surface; a gate layer located on a side of the gate insulating layer away from the first surface; the first dielectric layer is positioned on one side of the grid electrode layer away from the first surface; The semiconductor device further comprises a plurality of first contact holes and a second dielectric layer, wherein the first contact holes penetrate through the gate insulating layer, the gate layer and the first dielectric layer and expose the side wall of the gate insulating layer, the side wall of the gate layer and the side wall of the first dielectric layer, the second dielectric layer is located on the side wall of the first contact holes, the second dielectric layer located in the same first contact holes forms second contact holes, and the second contact holes expose at least part of the surface of the first area located on the first surface.
  2. 2. The semiconductor device of claim 1, wherein the second dielectric layer comprises a first sidewall and a second sidewall on a side of the first sidewall away from the sidewall of the first contact hole, the first sidewall comprises an undoped oxide layer, and the second sidewall comprises a doped oxide layer.
  3. 3. The semiconductor device according to claim 1, wherein a height of the second dielectric layer is the same as a depth of the first contact hole in a thickness direction of the semiconductor device.
  4. 4. A method of manufacturing a semiconductor device, comprising: The method comprises the steps of providing an epitaxial structure, wherein the epitaxial structure comprises a semiconductor body, a gate insulating material layer, a gate material layer and a first dielectric material layer which are sequentially laminated on the semiconductor body, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a first area, a well area and a second area, the gate insulating material layer is positioned on the first surface, the first area is of a first conductivity type and is positioned on the first surface, the well area is of a second conductivity type and is positioned between the first area and the second area, and the second area is of the first conductivity type; Patterning the first dielectric material layer, the gate material layer and the gate insulating material layer to form a first dielectric layer, a gate layer and a gate insulating layer, and forming a plurality of first contact holes; Forming a second dielectric material layer, wherein the second dielectric material layer fills the first contact hole and covers the first dielectric layer, a third contact hole corresponding to the first contact hole is formed in the second dielectric material layer, the orthographic projection of the third contact hole on the second surface is positioned in the orthographic projection of the first contact hole on the second surface along the thickness direction of the semiconductor device, and the orthographic projection area of the third contact hole on the second surface is smaller than the orthographic projection area of the first contact hole on the second surface; The second dielectric layer is positioned on the side wall of the first contact hole, the second dielectric layer positioned on the same first contact hole forms the second contact hole, and the second contact hole exposes at least part of the surface of the first area positioned on the first surface.
  5. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the forming the second dielectric layer comprises: Forming a first sub-dielectric layer, wherein the first sub-dielectric layer comprises an undoped oxide layer; And forming a second sub-dielectric layer covering the first sub-dielectric layer, wherein the second sub-dielectric layer comprises a doped oxide layer, and the thickness of the second sub-dielectric layer is larger than that of the first sub-dielectric layer.
  6. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a thickness of the second sub-dielectric layer is greater than or equal to five times a thickness of the first sub-dielectric layer.
  7. 7. The method of manufacturing a semiconductor device according to claim 4, wherein patterning the first dielectric material layer, the gate material layer, and the gate insulating material layer to form a first dielectric layer, a gate layer, and a gate insulating layer, and forming a plurality of first contact holes comprises: patterning the first dielectric material layer by using a first etching gas, wherein the etching selection ratio of the first etching gas to the first dielectric material layer and the grid material layer is greater than 1; Patterning the gate material layer by using a second etching gas, wherein the etching selection ratio of the second etching gas to the gate material layer and the gate insulating material layer is greater than 1; and patterning the grid insulating material layer by using a third etching gas, wherein the etching selectivity ratio of the third etching gas to the grid insulating material layer and the semiconductor body is greater than 1.
  8. 8. The method of manufacturing a semiconductor device according to claim 4, wherein the thinning the second dielectric material layer to form the second dielectric layer and the second contact hole further comprises: exposing a surface of the first dielectric layer remote from the second surface.
  9. 9. A power module comprising a substrate and at least one semiconductor device according to any of claims 1-3, said substrate being arranged to carry said semiconductor device.
  10. 10. A power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit comprising a circuit board and at least one semiconductor device according to any one of claims 1-3, the semiconductor device being electrically connected to the circuit board.
  11. 11. A vehicle comprising a load and the power conversion circuit according to claim 10, wherein the power conversion circuit is configured to convert alternating current into direct current, alternating current into alternating current, direct current into direct current, or direct current into alternating current, and then input the alternating current into the load.

Description

Semiconductor device, manufacturing method thereof, power module, power conversion circuit and vehicle Technical Field The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, a power module, a power conversion circuit, and a vehicle. Background Wide band gap semiconductor materials such as silicon carbide are widely used in the fields of power electronics, automobiles, aerospace and the like due to their excellent high temperature performance, chemical stability and electronic characteristics. The silicon carbide Metal-Oxide-semiconductor field effect transistor (MOSFET) in the related art has the advantages of large current density, small cell spacing and the like. The transistor needs to make a Contact (CT) hole in the interlayer dielectric layer, and the source electrode and the epitaxial layer are connected through the Contact hole. In the related art, a contact hole is manufactured in an overlay mode. However, when the cell size of the transistor is small, so that the size of the contact hole is close to the capacity limit of the photolithography machine, overlay deviation may occur in the contact hole, that is, the contact hole is located at a larger position, so that the contact hole is opened above the gate electrode to cause a short circuit between the source electrode and the gate electrode, or the contact hole is located at a larger position to cause poor performance of the semiconductor device. Disclosure of Invention The invention provides a semiconductor device, a preparation method thereof, a power module, a power conversion circuit and a vehicle, which are used for solving the problem of larger contact hole position deviation. According to an aspect of the present invention, there is provided a semiconductor device including: A semiconductor body including oppositely disposed first and second surfaces, the semiconductor body further including a first region disposed of a first conductivity type and located on the first surface, a well region disposed of a second conductivity type and located between the first and second regions, and a second region disposed of the first conductivity type; a gate insulating layer located on the first surface; a gate layer located on a side of the gate insulating layer away from the first surface; the first dielectric layer is positioned on one side of the grid electrode layer away from the first surface; The semiconductor device further comprises a plurality of first contact holes and a second dielectric layer, wherein the first contact holes penetrate through the gate insulating layer, the gate layer and the first dielectric layer and expose the side wall of the gate insulating layer, the side wall of the gate layer and the side wall of the first dielectric layer, the second dielectric layer is located on the side wall of the first contact holes, the second dielectric layer located in the same first contact holes forms second contact holes, and the second contact holes expose at least part of the surface of the first area located on the first surface. Optionally, the second dielectric layer comprises a first side wall and a second side wall located on one side of the first side wall away from the side wall of the first contact hole, wherein the first side wall comprises an undoped oxide layer, and the second side wall comprises a doped oxide layer. Optionally, the height of the second dielectric layer is the same as the depth of the first contact hole along the thickness direction of the semiconductor device. According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: The method comprises the steps of providing an epitaxial structure, wherein the epitaxial structure comprises a semiconductor body, a gate insulating material layer, a gate material layer and a first dielectric material layer which are sequentially laminated on the semiconductor body, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, the semiconductor body further comprises a first area, a well area and a second area, the gate insulating material layer is positioned on the first surface, the first area is of a first conductivity type and is positioned on the first surface, the well area is of a second conductivity type and is positioned between the first area and the second area, and the second area is of the first conductivity type; Patterning the first dielectric material layer, the gate material layer and the gate insulating material layer to form a first dielectric layer, a gate layer and a gate insulating layer, and forming a plurality of first contact holes; Forming a second dielectric material layer, wherein the second dielectric material layer fills the first contact hole and covers the first dielectric layer, a third contact hole corresponding to t