CN-122002862-A - Wide forbidden band semiconductor device

Abstract

The application discloses a wide-bandgap semiconductor device which can be used in the field of semiconductors and comprises a P-type column region, an N-type column region, a P-type buried layer, a P-type connecting layer, a grid electrode and a source electrode, wherein the P-type column region and the N-type column region are alternately arranged along a first direction, the P-type column region, the P-type buried layer, the P-type connecting layer and the source electrode are arranged along a second direction, the P-type connecting layer is in contact with the source electrode, the first direction is perpendicular to the second direction, the N-type column region, the grid electrode and the source electrode are arranged along the second direction, the P-type buried layer and the P-type connecting layer are intermittently distributed in a third direction, any P-type buried layer is electrically connected with at least one P-type connecting layer in a three-dimensional space, and any P-type column region is electrically connected with at least one P-type buried layer in a three-dimensional space, and the third direction is perpendicular to the first direction and the second direction. Therefore, an electric connection path of the P-type column region, the P-type buried layer, the P-type connection layer and the source electrode is constructed, and the dynamic resistance loss of the device is effectively reduced.

Inventors

• YUAN JUN
• WU YANGYANG
• CHEN WEI
• CHENG ZHIJIE

Assignees

• 湖北九峰山实验室

Dates

Publication Date

20260508

Application Date

20260211

Claims (13)

1. 1. The wide bandgap semiconductor device is characterized by comprising a P-type column region, an N-type column region, a P-type buried layer, a P-type connecting layer, a grid and a source electrode; The P-type column regions and the N-type column regions are alternately arranged along a first direction; The P-type column region, the P-type buried layer, the P-type connecting layer and the source electrode are arranged along a second direction, and the P-type connecting layer is contacted with the source electrode; The N-type column region, the grid electrode and the source electrode are arranged along a second direction; the P-type buried layers and the P-type connecting layers are intermittently distributed in a third direction, any one of the P-type buried layers is electrically connected with at least one P-type connecting layer in a three-dimensional space, any one of the P-type column regions is electrically connected with at least one of the P-type buried layers in the three-dimensional space, and the third direction is perpendicular to the first direction and the second direction.
2. 2. The device of claim 1, wherein the P-type pillar region, the P-type buried layer, the P-type connection layer, and the source electrode are stacked in sequence in a second direction within a first cross section of the device; the P-type connecting layer wraps the grid electrode, and the P-type connecting layer is in contact with the bottom of the source electrode, the top of the N-type column region and the top of the P-type buried layer.
3. 3. The device of claim 1, wherein in a second cross-section of the device, the P-type pillar region, the P-type buried layer, the P-type connection layer, and the source electrode are stacked in sequence in a second direction; The device further comprises a current expansion layer, a P-type base region and an N-type source region which are sequentially stacked along the second direction; The current expansion layer is positioned at the bottom of the grid electrode and is contacted with the N-type column region, and the P-type base region and the N-type source region are positioned between the P-type connecting layer and the grid electrode; the N-type source region is in contact with the source electrode, and the P-type base region is in contact with the current expansion layer.
4. 4. The device of claim 3 wherein either side sidewall of the gate is in contact with the P-type connection layer.
5. 5. The device of claim 1, wherein in a third cross-section of the device, the P-type pillar region and the P-type buried layer are stacked in sequence in a second direction; The device further comprises a current expansion layer, a P-type base region and an N-type source region which are sequentially stacked along the second direction; the current expansion layer is positioned at the bottom of the grid electrode; one side of the current expansion layer, which is away from the grid electrode, is contacted with the P-type buried layer and the N-type column region, and one side of the current expansion layer, which is close to the grid electrode, is contacted with the P-type base region; The N-type source region is in contact with the source electrode.
6. 6. The device of claim 1, wherein in a fourth cross-section of the device, the device further comprises a current spreading layer, a P-type base region, and an N-type source region; The P-type column region, the current expansion layer, the P-type base region and the N-type source region are sequentially stacked along a second direction; the current expansion layer is positioned at the bottom of the grid electrode; one side of the current expansion layer, which is away from the grid electrode, is contacted with the P-type column region and the N-type column region, and one side of the current expansion layer, which is close to the grid electrode, is contacted with the P-type base region; The N-type source region is in contact with the source electrode.
7. 7. The device of claim 1, wherein in a fifth cross-section of the device, the device further comprises a current spreading layer, a P-type base region, and an N-type source region; The side wall of one side of the N-type column region is in contact with the P-type column region, and the P-type column region, the current expansion layer, the P-type base region and the N-type source region are sequentially stacked along a second direction; The other side wall of the N-type column region is in contact with the P-type column region and the P-type buried layer, and the P-type column region, the P-type buried layer and the P-type connecting layer are sequentially stacked along a second direction; the current expansion layer is positioned at the bottom of the grid electrode, and is contacted with the P-type column region and the N-type column region at the side without the P-type connecting layer; and the P-type connecting layer and the N-type source region are in contact with the source electrode.
8. 8. The device of claim 1, wherein in a sixth cross-section of the device, the device further comprises a current spreading layer, a P-type base region, and an N-type source region; The voltage-resistant layer, the P-type buried layer, the current expansion layer, the P-type base region, the N-type source region and the source electrode which are formed by the P-type column region and the N-type column region are sequentially stacked along a second direction; the current expansion layer is positioned at the bottom of the grid electrode, and the N-type source region is in contact with the source electrode; And one side of the current expansion layer, which is away from the grid electrode, is contacted with the P-type buried layer, and the P-type buried layer covers the top of the pressure-resistant layer.
9. 9. The device according to any one of claims 3 to 8, further comprising an N-type doped region; The N-type doped region is positioned in the current expansion layer and/or the N-type column region between two adjacent P-type buried layers.
10. 10. The device of claim 1, wherein a side of the P-type buried layer proximate the source electrode is in contact with a side of the gate electrode facing away from the source electrode.
11. 11. The device of claim 1, wherein the P-type connection layer is formed on the sidewall and bottom of the source auxiliary trench by ion implantation, and the source electrode is filled in the source auxiliary trench.
12. 12. The device of claim 1, further comprising a P-type shield layer; the P-type shielding layer is positioned on one side of the grid electrode, which is away from the source electrode.
13. 13. The device of claim 1, further comprising an N-type drift layer; the N-type drift layer is positioned on one side of the P-type column region and one side of the N-type column region, which is away from the source electrode.

Description

Wide forbidden band semiconductor device Technical Field The application relates to the technical field of semiconductors, in particular to a wide bandgap semiconductor device. Background With the rapid development of the wide bandgap semiconductor technology, the superjunction technology becomes a key means for breaking the one-dimensional performance limit of the wide bandgap semiconductor device and improving the conduction performance of the device. At present, a wide-bandgap superjunction MOSFET device with switching characteristics is prepared, wherein a superjunction columnar structure is prepared first, then epitaxy is performed again on the top of the superjunction columnar structure, and the MOSFET structure is prepared in a new epitaxial layer. On the one hand, however, the impurity atoms cannot be rapidly diffused in the wide band gap semiconductor material due to the characteristic limitation of the wide band gap semiconductor material such as silicon carbide, and are difficult to form deeper doping in an ion implantation mode, and on the other hand, a new P-type doping region needs to be introduced for connecting a source electrode and a P-type column region in a super-junction columnar structure, and the newly introduced P-type doping region can squeeze a current transmission path, so that the on-resistance of the device is increased. Therefore, in order to give consideration to the on-resistance of the device, it is difficult to realize the comprehensive connection between each P-type column region and the source electrode positioned on the surface of the device, part of the P-type column regions can become floating P-columns due to space shielding, and in the switching process of the device, the floating P-columns cannot timely supplement holes, so that the dynamic resistance loss of the device is greatly increased. Thus, how to reduce the dynamic resistance loss of the device becomes a problem to be solved. Disclosure of Invention Based on the above problems, the present application provides a wide bandgap semiconductor device having low dynamic resistance loss. The embodiment of the application discloses the following technical scheme: The embodiment of the application provides a wide band gap semiconductor device, which comprises a P-type column region, an N-type column region, a P-type buried layer, a P-type connecting layer, a grid electrode and a source electrode, wherein the P-type column region is arranged on the N-type column region; The P-type column regions and the N-type column regions are alternately arranged along a first direction; The P-type column region, the P-type buried layer, the P-type connecting layer and the source electrode are arranged along a second direction, and the P-type connecting layer is contacted with the source electrode; The N-type column region, the grid electrode and the source electrode are arranged along a second direction; the P-type buried layers and the P-type connecting layers are intermittently distributed in a third direction, any one of the P-type buried layers is electrically connected with at least one P-type connecting layer in a three-dimensional space, any one of the P-type column regions is electrically connected with at least one of the P-type buried layers in the three-dimensional space, and the third direction is perpendicular to the first direction and the second direction. Optionally, in the first cross section of the device, the P-type pillar region, the P-type buried layer, the P-type connection layer, and the source electrode are stacked in sequence in a second direction; the P-type connecting layer wraps the grid electrode, and the P-type connecting layer is in contact with the bottom of the source electrode, the top of the N-type column region and the top of the P-type buried layer. Optionally, in the second cross section of the device, the P-type pillar region, the P-type buried layer, the P-type connection layer, and the source electrode are stacked in sequence in a second direction; The device further comprises a current expansion layer, a P-type base region and an N-type source region which are sequentially stacked along the second direction; The current expansion layer is positioned at the bottom of the grid electrode and is contacted with the N-type column region, and the P-type base region and the N-type source region are positioned between the P-type connecting layer and the grid electrode; the N-type source region is in contact with the source electrode, and the P-type base region is in contact with the current expansion layer. Optionally, sidewalls of either side of the gate are in contact with the P-type connection layer. Optionally, in the third cross section of the device, the P-type pillar region and the P-type buried layer are stacked in sequence in the second direction; The device further comprises a current expansion layer, a P-type base region and an N-type source region which are sequentially stacked along th