CN-122002863-A - Power device resistant to single particle burning, preparation method thereof and chip

Abstract

The application belongs to the technical field of power devices, and provides a single particle burnout resistant power device, a preparation method thereof and a chip thereof, wherein a P-type well region is formed on an N-type drift region, a first gate oxide layer and a second gate oxide layer are respectively formed on two sides of the P-type well region, an N-type polysilicon layer is formed in the first gate oxide layer, a P-type polysilicon layer is formed in the second gate oxide layer, an N-type heavily doped region and a P-type heavily doped region are contacted with the P-type well region, the first electrode layer covers the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region and the P-type heavily doped region, and by introducing a P-type polysilicon source electrode, an MIS barrier is applied to the surface of the device, the surface electric field is adjusted, more electric field lines point to the trench source electrode, so that most holes drift to the surface of the trench source electrode to flow to the P-type heavily doped region, the phenomenon that holes accumulate on the gate electrode to induce gate penetration is avoided, and the problem that single particles fail in the device is solved.

Inventors

• LV HAITAO

Assignees

• 深圳天狼芯半导体有限公司

Dates

Publication Date

20260508

Application Date

20260402

Claims (10)

1. 1. A power device resistant to single event burn out, the power device comprising: a silicon carbide substrate and an N-type drift region formed on the front surface of the silicon carbide substrate; a first gate oxide layer and a second gate oxide layer formed on the N-type drift region; An N-type polysilicon layer formed in the first gate oxide layer; the P-type polycrystalline silicon layer is formed in the second gate oxide layer; The first gate oxide layer and the second gate oxide layer are respectively positioned at two sides of the P-type well region; The P-type heavily doped region is contacted with the second gate oxide layer, and the N-type heavily doped region is contacted with the first gate oxide layer; A first electrode layer in contact with the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region and the P-type heavily doped region; And a second electrode layer formed on the back surface of the silicon carbide substrate.
2. 2. The power device of claim 1, wherein the N-type heavily doped region and the P-type heavily doped region are formed on the P-type well region.
3. 3. The power device of claim 2, wherein two sides of the P-type well region are in contact with the first gate oxide layer and the second gate oxide layer, respectively.
4. 4. The power device of claim 1, wherein the P-type heavily doped region is formed between the N-type heavily doped region and the second gate oxide layer, the P-type heavily doped region also being formed between the P-type well region and the second gate oxide layer.
5. 5. The power device of claim 4, wherein the P-type heavily doped region further extends to a bottom of the second gate oxide layer.
6. 6. The power device of claim 4, wherein a depth of the second gate oxide is greater than a depth of the first gate oxide.
7. 7. The power device of any of claims 1-6, wherein the power device further comprises: the reinforcing layer comprises a plurality of reinforcing medium areas which are stacked, and the widths of the reinforcing medium areas gradually decrease from the second electrode layer to the first electrode layer.
8. 8. The power device of claim 7, wherein a plurality of said stiffening medium regions have an arithmetic progression of widths, or, The dielectric constants of the reinforcing medium areas gradually decrease from the second electrode layer to the first electrode layer.
9. 9. A method of manufacturing a power device according to any one of claims 1 to 8, comprising: Forming an N-type drift region on the front surface of the silicon carbide substrate; Etching two sides of the N-type drift region, and forming a first gate oxide layer and a second gate oxide layer on two sides of the N-type drift region respectively; Forming an N-type polycrystalline silicon layer on the first gate oxide layer, and forming a P-type polycrystalline silicon layer on the second gate oxide layer; The P-type well region is formed by an ion implantation process, and the N-type heavily doped region and the P-type heavily doped region are contacted with the P-type well region; the first gate oxide layer and the second gate oxide layer are respectively positioned at two sides of the P-type well region; Depositing a silicon oxide material to form a first gate oxide layer wrapping the N-type polycrystalline silicon layer and a second gate oxide layer wrapping the P-type polycrystalline silicon layer; and forming a first electrode layer covering the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region and the P-type heavily doped region, and forming a second electrode layer on the back surface of the silicon carbide substrate.
10. 10. A chip comprising a power device according to any of claims 1-8.

Description

Power device resistant to single particle burning, preparation method thereof and chip Technical Field The application belongs to the technical field of power devices, and particularly relates to a single-particle burnout resistant power device, a preparation method thereof and a chip. Background The Trench metal oxide semiconductor (Trench MOSFET) has become a core power device of a high-power electronic system in radiation environments such as aerospace, aviation, nuclear industry and the like by virtue of the advantages of low specific on-resistance, high current density and excellent high-frequency characteristics, and is a key basis for realizing equipment miniaturization and high efficiency. Under extreme working conditions such as space high-energy heavy ions, proton irradiation and the like, the power device is easily affected by a single event effect, wherein Single Event Burnout (SEB) is a main form for causing the sudden failure of a Trench MOSFET, once the device is permanently damaged, the system paralysis is directly caused, and the operation safety of equipment is seriously threatened. Compared with a planar gate structure, the Trench corners of the Trench MOSFET have obvious electric field concentration, and are easier to trigger the SEB effect under high-energy particle irradiation. However, in the related art, most of anti-SEB technologies are designed as planar gate devices, the adaptability is poor, the reinforcement means usually have the cost of sacrificing the on and off characteristics of the devices, the radiation resistance and the electrical performance of the device core are difficult to be considered, the application requirements of the radiation environment on the Trench MOSFET cannot be met, and the research and development of the efficient anti-SEB technology adapting to the structural characteristics of the SEB technology is very important. Disclosure of Invention In order to solve the technical problems, the embodiment of the application provides a power device resistant to single particle burnout, a preparation method thereof and a chip, and aims to optimize the threshold voltage of the device and improve the reliability of the device. An embodiment of the present application provides a power device resistant to single particle burnout, where the power device includes: a silicon carbide substrate and an N-type drift region formed on the front surface of the silicon carbide substrate; a first gate oxide layer and a second gate oxide layer formed on the N-type drift region; An N-type polysilicon layer formed in the first gate oxide layer; the P-type polycrystalline silicon layer is formed in the second gate oxide layer; The first gate oxide layer and the second gate oxide layer are respectively positioned at two sides of the P-type well region; The P-type heavily doped region is contacted with the second gate oxide layer, and the N-type heavily doped region is contacted with the first gate oxide layer; A first electrode layer in contact with the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region and the P-type heavily doped region; And a second electrode layer formed on the back surface of the silicon carbide substrate. In some embodiments, the N-type heavily doped region and the P-type heavily doped region are formed on the P-type well region. In some embodiments, two sides of the P-type well region are respectively contacted with the first gate oxide layer and the second gate oxide layer. In some embodiments, the P-type heavily doped region is formed between the N-type heavily doped region and the second gate oxide layer, the P-type heavily doped region also being formed between the P-type well region and the second gate oxide layer. In some embodiments, the P-type heavily doped region also extends to the bottom of the second gate oxide layer. In some embodiments, the depth of the second gate oxide is greater than the depth of the first gate oxide. In some embodiments, the power device further comprises: the reinforcing layer comprises a plurality of reinforcing medium areas which are stacked, and the widths of the reinforcing medium areas gradually decrease from the second electrode layer to the first electrode layer. In some embodiments, the plurality of reinforcing medium regions have widths in an arithmetic progression, or, The dielectric constants of the reinforcing medium areas gradually decrease from the second electrode layer to the first electrode layer. The second aspect of the embodiment of the present application further provides a method for manufacturing a power device according to any one of the foregoing embodiments, where the method includes: Forming an N-type drift region on the front surface of the silicon carbide substrate; Etching two sides of the N-type drift region, and forming a first gate oxide layer and a second gate oxide layer on two sides of the N-type drift region respectively; Forming an N-type polycrystallin