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CN-122002866-A - Transistor structure, vertical NAND flash memory and method

CN122002866ACN 122002866 ACN122002866 ACN 122002866ACN-122002866-A

Abstract

A transistor structure for a vertical NAND flash memory device is provided. The transistor structure includes a semiconductor channel layer, and first and second auxiliary layers disposed at two opposite sides of the semiconductor channel layer along a first axis, and each of the first and second auxiliary layers includes a first material having a first relative dielectric constant that is greater than 1 and less than 3.9. The transistor structure further includes a first dielectric layer disposed over the semiconductor channel layer, the first auxiliary layer, and the first auxiliary layer along a second axis perpendicular to the first axis, a charge storage layer disposed on the first dielectric layer, a second dielectric layer disposed on the charge storage layer, and a gate layer disposed on the second dielectric layer.

Inventors

  • D. Vilek
  • S. Lachiti
  • M. Rossmoren

Assignees

  • IMEC非营利协会

Dates

Publication Date
20260508
Application Date
20251103
Priority Date
20241105

Claims (10)

  1. 1. A transistor structure (10) for a vertical NAND flash memory device, wherein the transistor structure (10) comprises: a semiconductor channel layer (12); A first auxiliary layer (13-1) and a second auxiliary layer (13-2) arranged on two opposite sides of the semiconductor channel layer (12) along a first axis, wherein each of the first auxiliary layer (13-1) and the second auxiliary layer (13-2) comprises a first material having a first relative permittivity, the first relative permittivity being greater than 1 and lower than 3.9; -a first dielectric layer (14) arranged over the semiconductor channel layer (12), the first auxiliary layer (13-1) and the second auxiliary layer (13-2) along a second axis perpendicular to the first axis; A charge storage layer (15) disposed on the first dielectric layer (14); A second dielectric layer (16) arranged on the charge storage layer (15), and A gate layer (17) disposed on the second dielectric layer (16).
  2. 2. The transistor structure (10) of claim 1, wherein: A first auxiliary layer (13-1) extending into the first dielectric layer (14) along the second axial portion, and/or The second auxiliary layer (13-2) extends partially into the first dielectric layer (14) along the second axis.
  3. 3. The transistor structure (10) according to claim 1 or 2, wherein: The first material is or includes air, or The first material comprises a porous material.
  4. 4. The transistor structure (10) according to any of the preceding claims, wherein: the first dielectric layer (14) includes a second material having a second relative permittivity that is greater than the first relative permittivity.
  5. 5. The transistor structure (10) according to any of the preceding claims, wherein: The cross-section of the semiconductor channel layer (12) in the region under the first dielectric layer (14) comprises a rectangle or trapezoid or triangle.
  6. 6. The transistor structure (10) according to any of the preceding claims, further comprising: A first spacer layer (31) arranged between the first auxiliary layer (13-1) and the semiconductor channel layer (12) along the first axis, and/or A second spacer layer (32) arranged along the first axis between the semiconductor channel layer (12) and the second auxiliary layer (13-2).
  7. 7. The transistor structure (10) of claim 6, wherein: The first spacer layer (31) and/or the second spacer layer (32) comprises a third material having a third relative permittivity, and the third relative permittivity is greater than the first relative permittivity and less than the second relative permittivity.
  8. 8. The transistor structure (10) of claim 7, wherein: the third material includes SiO 2 .
  9. 9. A vertical NAND flash memory (100, 110) comprising one or more transistor structures (10) according to any of the preceding claims.
  10. 10. A method (90) for fabricating a transistor structure (10) of a vertical NAND flash memory, the method comprising: Forming (91) a semiconductor channel layer (12); Forming (92) a first auxiliary layer (13-1) and a second auxiliary layer (13-2) at two opposite sides of the semiconductor channel layer (12) along a first axis, wherein each of the first auxiliary layer (13-1) and the second auxiliary layer (13-2) comprises a first material having a first relative permittivity, the first relative permittivity being greater than 1 and lower than 3.9; -forming (93) a first dielectric layer (14) over the semiconductor channel layer (12), the first auxiliary layer (13-1) and the second auxiliary layer (13-2) along a second axis perpendicular to the first axis; -forming (94) a charge storage layer (15) on the first dielectric layer (14); Forming (95) a second dielectric layer (16) over the charge storage, and A gate layer (17) is formed (96) on the second dielectric layer (16).

Description

Transistor structure, vertical NAND flash memory and method Technical Field The present disclosure provides a transistor structure for a vertical NAND flash memory, and a method for processing the transistor structure. A vertical NAND flash memory including one or more transistor structures is also provided. Background Flash memory is a type of non-volatile memory that can be electrically programmed and erased. NAND flash is a special type of flash in which individual memory cells are connected in series in the form of NAND gates. NAND flash memory with a three-dimensional (3D) architecture, i.e., NAND flash memory with vertically arranged memory cells, is commonly referred to as 3D NAND or vertical NAND. NAND flash memory is capable of storing information in a nonvolatile manner in the form of charge carriers (electrons or holes), either in a charge trapping layer or in a floating gate that is part of a flash memory cell transistor. The concentration of stored charge carriers corresponds to the bits of information stored in the memory and can be read by the resulting threshold voltage shift of the flash memory cell transistor. Quantum tunneling is used to change the concentration of charge carriers, thereby writing/erasing information to/from the memory. The size of the flash cells of vertical NAND flash memories has been scaled down in successive generations of technology to increase the bit density. Production technology has transitioned from planar devices to vertical 3D structures where the memory strings consist of cylindrical memory holes, along which Kong Duidie flash cells, also known as fully-surrounding Gate (GAA) strings, are located. These strings can be fabricated by first depositing a stack of alternating layers, then etching the memory holes, and then filling the memory holes with memory and channel layers. This 3D architecture allows increasing the bit density by adding more cells to the string instead of scaling the cell size. However, as the aspect ratio of the memory holes increases, the etching process becomes more challenging, ultimately limiting the number of cells on the string. To further increase the bit density, efforts have focused on shrinking the vertical cell pitch, including the flash memory cell gate length and the inter-gate pitch. However, this increases the interference between cells and reduces gate control for carrier injection. Or 3D trench cell architectures have been developed for vertical NAND flash memories. Unlike the cylindrical holes in conventional GAA structures, the memory strings in 3D trench cell architectures are fabricated in elongated trenches, where each trench accommodates multiple strings, with the trenches separated by insulating oxide material. This allows strings to be packed very tightly together, increasing bit density. Transitioning to 3D trench cells with proportional vertical spacing enables large bit densities, but also significantly reduces memory operation of the cell. The flash memory cells in the trenches are flat and therefore do not benefit from the so-called "curvature effect" of the GAA cells. In a cylindrical GAA cell, the tunnel oxide has a smaller radius than the blocking oxide, which ensures that the electric field in the tunnel oxide is larger than in the blocking oxide for a given gate voltage. This facilitates injection of charge carriers through the tunnel oxide relative to their escape through the blocking oxide and thus improves memory operation. Furthermore, since the memory stack is planar in the 3D trench cell architecture, the electric field is more uniformly distributed over the tunnel and blocking oxide. Similar to GAA structures, the memory operation of 3D trench cell structures further degrades as the vertical cell pitch shrinks. This, in combination with the flat cell geometry, may lead to a deterioration of the overall memory performance. Disclosure of Invention It is therefore an object of the present disclosure to provide a 3D trench NAND flash memory structure with improved performance, and an improved method for handling the memory structure. In particular, the above-mentioned disadvantages should be avoided. This object and other advantages are achieved by the embodiments provided in the independent claims. Advantageous implementations are further defined in the dependent claims. Hereinafter of the present disclosure, the terms "vertical NAND flash memory" and "3D trench NAND flash memory structure" are used interchangeably. That is, the present disclosure relates to a vertical NAND flash memory having a trench structure, not a GAA structure. According to a first aspect, the present disclosure relates to a transistor structure for a vertical NAND flash memory device. The transistor structure includes a semiconductor channel layer, and first and second auxiliary layers disposed at two opposite sides of the semiconductor channel layer along a first axis, wherein each of the first and second auxiliary layers incl