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CN-122002867-A - Method for preparing semiconductor structure

CN122002867ACN 122002867 ACN122002867 ACN 122002867ACN-122002867-A

Abstract

The invention provides a preparation method of a semiconductor structure, which comprises the steps of providing a substrate, forming an epitaxial layer on the substrate, sequentially forming a polycrystalline silicon layer and an amorphous carbon layer on the epitaxial layer from bottom to top, forming a patterned photoresist layer on the amorphous carbon layer, etching the amorphous carbon layer by taking the patterned photoresist layer as a mask to form an opening exposing the polycrystalline silicon layer, and performing an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening. The invention can shorten the processing time and reduce the preparation cost.

Inventors

  • HUANG TILONG

Assignees

  • 芯联越州集成电路制造（绍兴）有限公司

Dates

Publication Date
20260508
Application Date
20260209

Claims (10)

  1. 1. A method of fabricating a semiconductor structure, comprising: providing a substrate, wherein an epitaxial layer is formed on the substrate; sequentially forming a polycrystalline silicon layer and an amorphous carbon layer which are positioned on the epitaxial layer from bottom to top; forming a patterned photoresist layer on the amorphous carbon layer; Etching the amorphous carbon layer to form an opening exposing the polysilicon layer by using the patterned photoresist layer as a mask, and An ion implantation process is performed to form a doped region in the epitaxial layer below the bottom of the opening.
  2. 2. The method of manufacturing a semiconductor structure of claim 1, wherein the amorphous carbon layer has a thickness greater than a thickness of the polysilicon layer.
  3. 3. The method of manufacturing a semiconductor structure according to claim 2, wherein the amorphous carbon layer has a thickness of 1.8 μm to 2.2 μm.
  4. 4. The method of manufacturing a semiconductor structure according to claim 2, wherein the thickness of the polysilicon layer is 0.45 μm to 0.55 μm.
  5. 5. The method of manufacturing a semiconductor structure of claim 1, wherein the polysilicon layer is an undoped polysilicon layer.
  6. 6. The method of manufacturing a semiconductor structure of claim 1, wherein etching the amorphous carbon layer forms an opening exposing the polysilicon layer, simultaneously etching portions of the polysilicon layer such that the opening extends into the polysilicon layer.
  7. 7. The method of manufacturing a semiconductor structure according to claim 6, wherein the thickness of the polysilicon layer is etched to be 8 nm-12 nm.
  8. 8. The method of claim 1, wherein the patterned photoresist layer is removed after etching the amorphous carbon layer to form an opening exposing the polysilicon layer.
  9. 9. The method of manufacturing a semiconductor structure of claim 1, wherein a depth of the doped region is less than a thickness of the epitaxial layer.
  10. 10. The method of manufacturing a semiconductor structure according to claim 1, wherein the doping type of the doped region is P-type or N-type.

Description

Method for preparing semiconductor structure Technical Field The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure. Background In the preparation of a semiconductor structure, a P-type or N-type doped region needs to be formed in an epitaxial layer, a multi-layer dielectric structure is generally used as a barrier layer, the number of film layers of the multi-layer dielectric structure is generally greater than or equal to 3 layers, then the multi-layer dielectric structure is etched step by step to define an implanted region, and then the multi-layer dielectric structure is used as the barrier layer to perform ion implantation on the epitaxial layer so as to form the P-type or N-type doped region in the epitaxial layer. However, forming the multi-layer dielectric structure requires multiple film growth processes, and etching the multi-layer dielectric structure step by step requires multiple etching processes, which has long process cycle and high preparation cost. Disclosure of Invention The invention aims to provide a preparation method of a semiconductor structure, which can shorten the processing time and reduce the preparation cost. In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, wherein an epitaxial layer is formed on the substrate; sequentially forming a polycrystalline silicon layer and an amorphous carbon layer which are positioned on the epitaxial layer from bottom to top; forming a patterned photoresist layer on the amorphous carbon layer; Etching the amorphous carbon layer to form an opening exposing the polysilicon layer by using the patterned photoresist layer as a mask, and An ion implantation process is performed to form a doped region in the epitaxial layer below the bottom of the opening. Optionally, the amorphous carbon layer has a thickness greater than a thickness of the polysilicon layer. Optionally, the thickness of the amorphous carbon layer is 1.8-2.2 μm. Optionally, the thickness of the polysilicon layer is 0.45-0.55 μm. Optionally, the polysilicon layer is an undoped polysilicon layer. Optionally, etching the amorphous carbon layer to form an opening exposing the polysilicon layer simultaneously etches portions of the polysilicon layer such that the opening extends into the polysilicon layer. Optionally, the thickness of the polysilicon layer is 8 nm-12 nm. Optionally, after etching the amorphous carbon layer to form an opening exposing the polysilicon layer, removing the patterned photoresist layer. Optionally, the depth of the doped region is less than the thickness of the epitaxial layer. Optionally, the doping type of the doped region is P-type or N-type. The preparation method of the semiconductor structure comprises the steps of providing a substrate, forming an epitaxial layer on the substrate, sequentially forming a polycrystalline silicon layer and an amorphous carbon layer on the epitaxial layer from bottom to top, forming a patterned photoresist layer on the amorphous carbon layer, etching the amorphous carbon layer to form an opening exposing the polycrystalline silicon layer by taking the patterned photoresist layer as a mask, and performing an ion implantation process to form a doped region in the epitaxial layer below the bottom of the opening. According to the invention, only two film growth processes are needed, namely the polycrystalline silicon layer and the amorphous carbon layer are formed in sequence, so that the film growth process can be saved, and only one etching process is needed, namely the amorphous carbon layer is etched to form an opening exposing the polycrystalline silicon layer, so that the etching process can be saved, the processing time is shortened, and the preparation cost is reduced. Drawings Fig. 1 to 5 are schematic cross-sectional views of corresponding steps in a method for manufacturing a semiconductor structure. Fig. 6 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. Fig. 7 to 10 are schematic cross-sectional views illustrating corresponding steps in a method for manufacturing a semiconductor structure according to an embodiment of the present invention. Wherein, the reference numerals of fig. 1-5 are: 10-substrate, 20-epitaxial layer, 31-first oxide layer, 32-polysilicon layer, 33-second oxide layer, 40-patterned photoresist layer, 50-opening, 60-doped region. Reference numerals of fig. 7 to 10 are: 100-substrate, 200-epitaxial layer, 310-polysilicon layer, 320-amorphous carbon layer, 400-patterned photoresist layer, 500-opening, 600-doped region. Detailed Description Fig. 1 to 5 are schematic cross-sectional views of corresponding steps in a method for manufacturing a semiconductor structure. Referring to fig. 1, a substrate 10 is provided, an epitaxial layer 20 is formed on