CN-122002868-A - Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes an active region and a junction termination region each including a drain electrode, a first epitaxial layer of a first conductivity type disposed on the drain electrode, and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer. The junction termination region further includes a first junction termination region etched on a portion of the second epitaxial layer and a second junction termination region not etched. A field oxide layer is disposed on a portion of the first junction termination region. Doped regions of the second conductivity type are provided extending from under the field oxide layer to the second junction termination region.

Inventors

• Cao Yongxu
• LIN ZHIRONG
• JIN QIHUAN

Assignees

• 美格纳半导体有限公司

Dates

Publication Date

20260508

Application Date

20251022

Priority Date

20241101

Claims (20)

1. 1. A semiconductor device, comprising: An active region and a junction termination region, each of the active region and the junction termination region comprising: A drain electrode; a first epitaxial layer of a first conductivity type, the first epitaxial layer being disposed on the drain electrode, and A second epitaxial layer of the first conductivity type, the second epitaxial layer being disposed on the first epitaxial layer, Wherein the junction termination region further comprises a first junction termination region etched on a portion of the second epitaxial layer and a second junction termination region not etched, Wherein a field oxide layer is disposed on a portion of the first junction termination region, an Wherein a doped region of a second conductivity type is provided extending from under the field oxide layer to the second junction termination region.
2. 2. The semiconductor device according to claim 1, Wherein the doped region comprises: a lightly doped region of the second conductivity type disposed in the first junction termination region, and A heavily doped region of the second conductivity type, the heavily doped region being arranged to extend from the first junction termination region to the second junction termination region.
3. 3. The semiconductor device according to claim 2, Wherein the thickness of the heavily doped region is greater than the thickness of the lightly doped region.
4. 4. The semiconductor device according to claim 1, Wherein a surface of the field oxide layer is coplanar with a surface of a second epitaxial layer present in the second junction termination region.
5. 5. The semiconductor device of claim 1, further comprising: a body region of the second conductivity type, the body region being disposed between trench gates in the active region, Wherein the body region is connected to the doped region.
6. 6. The semiconductor device of claim 1, further comprising: A layer of a second conductivity type formed between the drain electrode and the first epitaxial layer.
7. 7. The semiconductor device according to claim 1, Wherein the junction termination region further comprises: a junction termination etch region disposed between the field oxide layer and the second junction termination region; a field plate insulating layer disposed on an inner upper surface and an outer upper surface of the junction termination etch region; A field plate disposed on the field plate insulating layer; an interlayer insulating layer disposed on the field plate, and A source electrode and a gate electrode formed on the interlayer insulating layer.
8. 8. A semiconductor device, comprising: An active region and a junction termination region, each of the active region and the junction termination region comprising: A drain electrode; a first epitaxial layer of a first conductivity type, the first epitaxial layer being disposed on the drain electrode, and A second epitaxial layer of the first conductivity type, the second epitaxial layer being disposed on the first epitaxial layer, Wherein the junction termination region further comprises a first junction termination region etched on a portion of the second epitaxial layer and a second junction termination region not etched, Wherein a field oxide layer is disposed on a portion of the first junction termination region, and Wherein doped regions of a second conductivity type having different thicknesses are disposed in the first junction termination region and the second junction termination region.
9. 9. The semiconductor device of claim 8, further comprising: a body region of the second conductivity type, the body region being formed between trench gates in the active region, Wherein the body region is connected to the doped region.
10. 10. The semiconductor device according to claim 8, Wherein the doped region comprises: a lightly doped region of the second conductivity type disposed on the first junction termination region, and The heavily doped region of the second conductivity type is disposed to extend from the first junction termination region to the second junction termination region and has a higher doping concentration than the lightly doped region of the second conductivity type.
11. 11. The semiconductor device according to claim 10, Wherein the thickness of the heavily doped region is greater than the thickness of the lightly doped region.
12. 12. The semiconductor device according to claim 10, Wherein the doping concentration of the lightly doped region gradually decreases toward the edge of the first junction termination region.
13. 13. The semiconductor device of claim 10, further comprising: a source electrode in electrical contact with the heavily doped region; a field plate disposed on a portion of the heavily doped region and on the lightly doped region, and A gate electrode electrically contacting the field plate.
14. 14. The semiconductor device of claim 10, further comprising: A layer of a second conductivity type formed between the drain electrode and the first epitaxial layer.
15. 15. A method of fabricating a semiconductor device comprising an active region and a junction termination region, the method comprising: forming a first epitaxial layer of a first conductivity type on a semiconductor substrate of the first conductivity type; Forming a second epitaxial layer of the first conductivity type on the first epitaxial layer; etching an upper surface portion of the second epitaxial layer in the junction termination region; Performing a first ion implantation of a second conductivity type into both the etched junction termination region and the unetched junction termination region to form a first ion implantation region; Performing ion implantation of a second ion of the second conductivity type into a portion of both the etched junction termination region and the unetched junction termination region after the first ion implantation to form a second ion implantation region, and A field oxide layer is formed on a portion of the etched junction termination region by a thermal oxidation process.
16. 16. The method according to claim 15, Wherein ions implanted during the formation of the field oxide layer are diffused to form doped regions of the second conductivity type.
17. 17. The method according to claim 15, Wherein mask patterns used during formation of the first ion implantation region are formed such that a pitch between the mask patterns gradually decreases toward a chip edge.
18. 18. The method according to claim 15, Wherein the concentration of ions of the second conductivity type formed during the first ion implantation and the second ion implantation is the same.
19. 19. The method of claim 15, further comprising: forming a junction termination etch region after formation of the field oxide layer; forming a field plate insulating layer in the junction termination etch region; forming a field plate on the field plate insulating layer; forming an interlayer insulating layer on the field plate, and A portion of the interlayer insulating layer is etched to form a gate electrode in contact with the field plate and a source electrode in contact with the doped region.
20. 20. The method of claim 15, further comprising: Performing a polishing process on a bottom surface of the semiconductor substrate; performing a second conductivity type ion implantation process after the polishing process to form a layer of the second conductivity type, and A drain electrode is formed on a bottom surface of the layer.

Description

Semiconductor device and method of manufacturing the same Cross Reference to Related Applications The present application claims the benefit of korean patent application No. 10-2024-0153615, filed on 1 month 11 of 2024, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field The present disclosure relates to a semiconductor device capable of achieving more stable withstand voltage than conventional techniques and a method for manufacturing the semiconductor device. Background Power semiconductor devices such as MOSFETs (metal oxide semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors) are mainly used as semiconductor switching devices in power electronics applications. Among these power semiconductor devices, IGBTs can be classified into a horizontal structure in which a source (or emitter), a gate (or base), and a drain (or collector) are formed on an upper surface of a semiconductor substrate, and a vertical structure in which a source electrode and a gate electrode are formed on a top surface of the semiconductor substrate, and a drain electrode is formed on a bottom surface of the semiconductor substrate. For IGBT devices, it may be desirable to reduce the electric field peaks that occur at the substrate surface in the junction termination region. The maximum electric field peak usually occurs in the region of the junction termination where the equipotential ring exists. Under extremely high current and high voltage conditions, this region becomes significantly weakened, resulting in avalanche breakdown due to the large leakage current density under reverse bias. To prevent this, a technique of employing a P-ring structure or increasing the area of a junction termination region to reduce an electric field, such as by forming a plurality of P-type conductive rings, has been proposed. While the P-ring structure can reduce the electric field to some extent, it exhibits limitations when applied to high voltage devices. Alternatively, increasing the junction termination region may further reduce the electric field, but this approach may result in an undesirable increase in the device size, thereby presenting another problem. Such an IGBT semiconductor device must be able to disperse an electric field generated under reverse bias conditions, thereby reducing an electric field peak and ensuring a stable breakdown voltage associated with the withstand voltage of the semiconductor device. Accordingly, various methods have been proposed to improve the structure of the semiconductor device in order to improve the withstand voltage performance. The above information is presented merely as background information to aid in the understanding of the present disclosure. No decision was made, nor was an assertion, as to whether any during the term of office of the above volumes could be applied to the present disclosure as prior art. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. In one general aspect, a semiconductor device includes an active region and a junction termination region each including a drain electrode, a first epitaxial layer of a first conductivity type disposed on the drain electrode, and a second epitaxial layer of the first conductivity type disposed on the first epitaxial layer. The junction termination region further includes a first junction termination region etched on a portion of the second epitaxial layer and a second junction termination region not etched. A field oxide layer is disposed on a portion of the first junction termination region. Doped regions of the second conductivity type are provided extending from under the field oxide layer to the second junction termination region. The doped region may include a lightly doped region of the second conductivity type disposed in the first junction termination region and a heavily doped region of the second conductivity type disposed to extend from the first junction termination region to the second junction termination region. The thickness of the heavily doped region may be greater than the thickness of the lightly doped region. The surface of the field oxide layer may be coplanar with the surface of the second epitaxial layer present in the second junction termination region. The semiconductor device may further include a body region of the second conductivity type formed between the trench gates in the active region, wherein the body region is connected to the doped region. The semiconductor device may further include a layer of the second conductivity type formed between the drain electrode and the first epitaxial layer. The junction termination