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CN-122002869-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

CN122002869ACN 122002869 ACN122002869 ACN 122002869ACN-122002869-A

Abstract

A semiconductor device is provided with a drift layer (11) of a first conductivity type, a body layer (13) of a second conductivity type, a lower surface electrode (28), a gate wiring (21) connected to a gate electrode (20), a gate insulating film (19), and an upper surface electrode (26). A depletion region (16) of the first conductivity type depleted in a state where a voltage between the lower surface electrode and the upper surface electrode is 0V is formed in a portion of the surface layer portion on the upper surface side of the body layer, which is located under the gate wiring. The depletion region is formed in a lower portion of at least a portion of the end portions of the gate wiring. The upper surface of the body layer is exposed from the depletion region in a lower portion of at least a part of the portion of the gate wiring on the inner side than the end portion.

Inventors

  • MITSUI SHUNSUKE
  • RYUTA SUZUKI

Assignees

  • 株式会社电装
  • 丰田自动车株式会社
  • 未来瞻科技株式会社

Dates

Publication Date
20260508
Application Date
20251022
Priority Date
20241108

Claims (10)

  1. 1. A semiconductor device is characterized by comprising: a drift layer of a first conductivity type; A body layer of a second conductivity type laminated on an upper surface of the drift layer; a lower surface electrode formed on a lower surface side of the drift layer; a gate wiring formed on the upper surface side of the body layer and connected to a gate electrode; a gate insulating film formed between the upper surface of the body layer and the gate wiring, and An upper surface electrode formed on an upper surface side of the body layer, A depletion region of the first conductivity type depleted in a state where a voltage applied between the lower surface electrode and the upper surface electrode is 0V is formed in a portion of the surface layer portion on the upper surface side of the body layer, which is located under the gate wiring, The depletion region is formed in a lower portion of at least a portion of the end portions of the gate wiring, An upper surface of the body layer is exposed from the depletion region in a lower portion of at least a part of the gate wiring on an inner side than an end portion.
  2. 2. The semiconductor device according to claim 1, wherein, In a direction parallel to the upper surface of the body layer, The width of the portion of the depletion region protruding outward of the gate wiring from the end of the gate wiring is set to X1, Let 0< X1<5 μm.
  3. 3. The semiconductor device according to claim 1, wherein, In a direction parallel to the upper surface of the body layer, The width of the portion overlapping the gate wiring in the depletion region is set to X2, The width of the gate wiring is set to X3, Let 0< X2< X3.
  4. 4. The semiconductor device according to claim 1, wherein, The thickness of the depletion region is set to Y1, The thickness of the bulk layer is set to Y2, Let 0< Y1< Y2.
  5. 5. The semiconductor device according to any one of claim 1 to 4, wherein, The acceptor density of the bulk layer is set to N A , The donor density of the depletion region is set to N D , The dielectric constant of SiC is set to epsilon SiC , The built-in potential of the depletion region is set to be phi bi , The basic charge is set to q and, The width of the depleted region in the direction from the bulk layer toward the center of the depletion region is set to W depl,n , The width W depl,n required for the global depletion of the depletion region is set to W depl,n1 , Satisfies the following equation 4 [ Number 4] 。
  6. 6. The semiconductor device according to any one of claim 1 to 4, wherein, The upper surface electrode is in contact with a contact portion formed in a surface layer portion of the body layer in the interior of a trench penetrating the gate insulating film, In a direction parallel to the upper surface of the body layer, An end of the gate wiring on the opposite side of the center portion of the gate wiring from the contact portion is set as a first end, an end of the gate wiring on the same side as the contact portion from the center portion of the gate wiring is set as a second end, The depletion region is formed only in a lower portion of the first end portion and the second end portion.
  7. 7. The semiconductor device according to any one of claim 1 to 4, wherein, The upper surface electrode is in contact with a contact portion formed in a surface layer portion of the body layer in the interior of a trench penetrating the gate insulating film, In a direction parallel to the upper surface of the body layer, An end of the gate wiring on the opposite side of the center portion of the gate wiring from the contact portion is set as a first end, an end of the gate wiring on the same side as the contact portion from the center portion of the gate wiring is set as a second end, The depletion region is formed only in a lower portion of the second end portion of the first end portion and the second end portion.
  8. 8. The semiconductor device according to any one of claim 1 to 4, wherein, The depletion region is formed along an end of the gate wiring and divided into a plurality of regions.
  9. 9. The semiconductor device according to any one of claim 1 to 4, wherein, The first conductivity type is n-type, The second conductivity type is p-type.
  10. 10. The semiconductor device according to any one of claim 1 to 4, wherein, The first conductivity type is p-type, The second conductivity type is n-type.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Technical Field The present invention relates to a semiconductor device. Background The semiconductor device provided in the MOSFET device and the like is configured such that, for example, a body layer is laminated on the upper surface of the drift layer, a drain electrode is formed on the lower surface side of the drift layer, and a gate wiring and a source electrode are formed on the upper surface side of the body layer. MOSFETs are abbreviations for Metal Oxide Semiconductor FIELD EFFECT transistors, i.e., metal oxide semiconductor field effect transistors. In such a semiconductor device, a displacement current flows to the body layer via the PN junction capacitance between the drift layer and the body layer at the time of recovery operation. At this time, the potential of the body layer increases due to the path resistance of the body layer, and a potential difference occurs between the gate wiring and the body layer. When the potential difference increases, a high electric field is applied to the gate insulating film formed between the body layer and the gate wiring, and breakdown is likely to occur. The semiconductor device described in patent document 1 includes a MOSFET element having a structure in which a p-type body layer is stacked on the upper surface of an n-type drift layer, and a p + -type region is formed on the upper surface side surface layer portion of the body layer so as to contact with a gate insulating film. The p + type region is formed in the entire region of the lower portion of the gate wiring in the surface layer portion of the body layer. In addition, the p + type region is covered on the side and the lower surface by an n + type region connected to the source potential, and the p type region and the p + type region of the body layer are separated by an n + type region. With this structure, penetration of the displacement current into the p + type region can be suppressed, and breakdown of the gate insulating film due to an increase in potential of the p + type region can be suppressed. Prior art literature Patent literature Patent document 1 Japanese patent application laid-open No. 2021-125638 Disclosure of Invention In the semiconductor device described in patent document 1, the p-type region is thinner than the p-type region in other portions at the lower portions of the p + -type region and the n + -type region, and thus the path resistance of the displacement current in the p-type region is larger than in other portions. Therefore, if the p + type region and the n + type region are formed entirely on the surface layer portion of the body layer under the gate wiring, the portion having a large path resistance increases, and therefore the temperature locally rises during the recovery operation, which may cause breakdown of the element. In view of the above, an object of the present disclosure is to provide a semiconductor device capable of improving recovery breakdown resistance. In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes a drift layer of a first conductivity type, a body layer of a second conductivity type stacked on an upper surface of the drift layer, a lower surface electrode formed on a lower surface side of the drift layer, a gate wiring formed on an upper surface side of the body layer and connected to the gate electrode, a gate insulating film formed between the upper surface of the body layer and the gate wiring, and an upper surface electrode formed on an upper surface side of the body layer. In a portion of the surface layer portion on the upper surface side of the body layer located below the gate wiring, a depletion region of the first conductivity type depleted in a state where a voltage applied between the lower surface electrode and the upper surface electrode is 0V is formed. The depletion region is formed in a lower portion of at least a part of the end portion of the gate wiring, and an upper surface of the body layer is exposed from the depletion region in a lower portion of at least a part of a portion of the gate wiring that is further inside than the end portion. The depletion region is hardly affected by the potential rise due to the displacement current flowing through the body layer. Therefore, when a depletion region is formed in the lower portion of the gate wiring, an electric field applied to the gate insulating film is reduced. In the vicinity of the end portion of the gate wiring, a higher electric field is easily applied to the gate insulating film than in the vicinity of the portion inside the end portion, and breakdown is easily generated. Therefore, by forming a depletion region in a lower portion of at least a part of an end portion of the gate wiring, breakdown of the gate insulating film can be suppressed. Further, by forming the upper surface of the body layer to be ex