CN-122002870-A - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

CN122002870ACN 122002870 ACN122002870 ACN 122002870ACN-122002870-A

Abstract

The semiconductor device includes a first conductive pressure-resistant holding layer and a super junction layer disposed in contact with an upper surface of the pressure-resistant holding layer. In the super junction layer, first regions of the first conductivity type and second regions of the second conductivity type are alternately and repeatedly arranged along the first direction. The second region includes a lower second region in contact with the pressure-resistant holding layer and an upper second region disposed in contact with an upper surface of the lower second region. The lower second region has a maximum width in the first direction, that is, a lower maximum width. The upper second region has a maximum width in the first direction, that is, an upper maximum width. The lower maximum width is larger than the upper maximum width. Regarding the density of the fixed charges at the time of depletion, the lower side second region is higher than the upper side second region.

Inventors

New Lin Zhiwen
Zhai Tengshun

Assignees

株式会社电装
丰田自动车株式会社
未来瞻科技株式会社

Dates

Publication Date: 20260508
Application Date: 20251103
Priority Date: 20241106

Claims (7)

1.A semiconductor device, characterized in that, The device is provided with: A voltage-resistant holding layer of the first conductivity type, and A super junction layer which is disposed in contact with the upper surface of the pressure-resistant holding layer and alternately and repeatedly includes first regions of a first conductivity type and second regions of a second conductivity type along a first direction, The second region has a lower second region contacting the pressure-resistant holding layer and an upper second region contacting the upper surface of the lower second region, The lower second region has a maximum width in the first direction or a lower maximum width, The upper second region has the maximum width in the first direction or upper maximum width, The lower maximum width is greater than the upper maximum width, The lower second region is higher than the upper second region in terms of density of fixed charges at the time of depletion.
2. The semiconductor device according to claim 1, wherein, The concentration of the second-conductivity-type impurity contained in the lower-side second region is higher than the concentration of the second-conductivity-type impurity contained in the upper-side second region.
3. The semiconductor device according to claim 1, wherein, The width of the first direction at the interface between the lower second region and the pressure-resistant holding layer is the lower maximum width.
4. The semiconductor device according to any one of claim 1 to 3, wherein, The first region includes a lower first region in contact with the pressure-resistant retaining layer and an upper first region in contact with an upper surface of the lower first region, The lower first region is disposed between the lower second regions adjacent to each other in the first direction, The upper first region is arranged between the upper second regions adjacent to each other in the first direction, The lower first region is lower than the upper first region in terms of density of fixed charges at the time of depletion.
5. The semiconductor device according to claim 4, wherein, The pressure-resistant holding layer has an overlap region overlapping the lower first region and the lower second region when the super junction layer is viewed from vertically above, The total amount of fixed charge at the time of depletion of the overlap region is set as the overlap region total amount of charge, The total amount of fixed charges at the time of depletion of the lower first region is set as the total amount of first region charges, When the total amount of fixed charges at the time of depletion of the lower second region is set as the total amount of charges of the second region, The second region charge total is more than the sum of the first region charge total and the overlap region charge total.
6. The semiconductor device according to any one of claim 1 to 3, wherein, The first conductivity type is n-type and the second conductivity type is p-type.
7. A semiconductor device, characterized in that, The device is provided with: A voltage-resistant holding layer of the first conductivity type, and A super junction layer which is disposed in contact with the upper surface of the pressure-resistant holding layer and alternately and repeatedly includes first regions of a first conductivity type and second regions of a second conductivity type along a first direction, The second region has a lower second region contacting the pressure-resistant holding layer and an upper second region contacting the upper surface of the lower second region, The lower second region has a maximum width in the first direction or a lower maximum width, The upper second region has the maximum width in the first direction or upper maximum width, The lower maximum width is greater than the upper maximum width, The concentration of the second-conductivity-type impurity contained in the lower-side second region is higher than the concentration of the second-conductivity-type impurity contained in the upper-side second region.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips Technical Field The technology disclosed in this specification relates to semiconductor devices. Background A semiconductor device is known that has a structure in which a super junction layer is stacked on top of a pressure-resistant holding layer (also referred to as a drift layer) that performs pressure-resistant sharing. The super junction layer is substantially completely depleted to form a depletion layer over a wide range, so that a sufficient withstand voltage can be ensured. Patent document 1 discloses an example of a semiconductor device having such a structure. Prior art literature Patent literature Patent document 1 U.S. patent application publication No. 2023-282705 specification Disclosure of Invention There are cases where it is difficult for the depletion layer to progress from the super junction layer into the drift layer. In this case, since the electric field in the drift layer is low, the withstand voltage of the drift layer may not be sufficiently ensured. In one embodiment of the semiconductor device disclosed in the present specification, the semiconductor device includes a voltage holding layer of a first conductivity type and a super junction layer disposed in contact with an upper surface of the voltage holding layer. In the super junction layer, first regions of the first conductivity type and second regions of the second conductivity type are alternately and repeatedly arranged along the first direction. The second region includes a lower second region in contact with the pressure-resistant holding layer, and an upper second region disposed in contact with an upper surface of the lower second region. The lower second region has a maximum width in the first direction, that is, a lower maximum width. The upper second region has a maximum width in the first direction, that is, an upper maximum width. The lower maximum width is larger than the upper maximum width. Regarding the density of the fixed charges at the time of depletion, the lower side second region is higher than the upper side second region. According to the above configuration, the lower second region is higher than the upper second region in terms of the density of the fixed charges at the time of depletion. Therefore, the depletion layer can be promoted to advance toward the pressure-resistant holding layer in contact with the lower second region in response to the increase in the density of the fixed charges in the lower second region. Since the electric field sharing of the voltage holding layer can be increased, the voltage resistance of the voltage holding layer can be improved. Drawings Fig. 1 is a main part sectional view of a semiconductor device. Fig. 2 is a partial enlarged view of the vicinity of the SJ layer. Fig. 3 is a partial enlarged view of the vicinity of the SJ layer in the semiconductor device of the comparative example. Fig. 4 is a partial enlarged view of the vicinity of the SJ layer in the semiconductor device of the present embodiment. Fig. 5 is a diagram illustrating a step of forming the SJ layer. Fig. 6 is a diagram illustrating a step of forming an SJ layer. Fig. 7 is a diagram illustrating a step of forming the SJ layer. Fig. 8 is a main part sectional view of the semiconductor device of the second embodiment. Fig. 9 is a diagram illustrating the effect of the second embodiment. Fig. 10 is a diagram illustrating a step of forming the SJ layer. Fig. 11 is a main part sectional view of the semiconductor device of the third embodiment. Fig. 12 is a view showing examples of various cross-sectional shapes of the lower second region. Detailed Description First embodiment Hereinafter, a semiconductor device disclosed in the present specification will be described with reference to the accompanying drawings. For clarity of illustration, only one of the components that are repeatedly arranged may be denoted by a reference numeral. As shown in fig. 1, the semiconductor device 1 is a power semiconductor device of a type called a MOSFET. The semiconductor device 1 includes a semiconductor substrate 10, a drain electrode 22 covering the lower surface of the semiconductor substrate 10, a source electrode 24 covering the upper surface of the semiconductor substrate 10, and a plurality of trench gates 30 provided in the upper layer of the semiconductor substrate 10. The material of the semiconductor substrate 10 is not particularly limited. In this embodiment silicon carbide. The n-type impurity is nitrogen, and the p-type impurity is aluminum. The semiconductor substrate 10 includes an n + -type drain region 11, an n - -type drift region 12, a super junction layer 14, a body region 15, a source region 16, and a body contact region 17. Hereinafter, the super junction layer may be simply referred to as "SJ layer". The drain region 11 is provided at a position exposed on the lower surface of the semiconductor substrate