CN-122002871-A - Growth substrate wafer for high performance GaN switching power device, epitaxial wafer using the same, and method of manufacturing the same

Abstract

A growth substrate wafer for a high performance GaN switching power device, an epitaxial wafer using the same, and a method of manufacturing the same are provided according to an embodiment of the present invention, the growth substrate wafer including a Si (111) growth substrate, a first AlN nucleation layer formed on the Si (111) growth substrate, and a plurality of SiOx protrusions (protrusions) discontinuously spaced apart on the first AlN nucleation layer, wherein a surface of the first AlN nucleation layer is exposed in a region between the plurality of SiOx protrusions.

Inventors

• SONG JUNWU
• Wen Zhijiong
• HAN YONGXUN
• Yin Hengshan

Assignees

• 威弗洛得有限公司

Dates

Publication Date

20260508

Application Date

20251105

Priority Date

20241105

Claims (11)

1. 1. A growth substrate wafer for a high performance GaN switching power device, the growth substrate wafer comprising: a Si (111) growth substrate; a first AlN nucleation layer formed on the Si (111) growth substrate, and A plurality of SiOx protrusions discontinuously spaced apart on the first AlN nucleation layer, wherein a surface of the first AlN nucleation layer is exposed in areas between the plurality of SiOx protrusions.
2. 2. The growth substrate wafer of claim 1, wherein the SiOx protrusions are lens-shaped, truncated-shaped, dome-shaped, conical-shaped, polygonal-shaped, or cubical-shaped in shape.
3. 3. The growth substrate wafer of claim 1, further comprising a SiNx protective film formed between the first AlN nucleation layer and the plurality of SiOx protrusions.
4. 4. An epitaxial wafer using the growth substrate wafer of claim 1, the epitaxial wafer comprising: a GaN-based merge growth layer grown from the exposed surface of the first AlN nucleation layer between the SiOx protrusions, covering the tops of the SiOx protrusions and merging with each other, and And the GaN HEMT device active layer is formed on the GaN-based combined growth layer.
5. 5. The epitaxial wafer of claim 4, wherein the GaN-based co-grown layer is an undoped GaN (uGaN) monolayer.
6. 6. The epitaxial wafer of claim 4, wherein the GaN-based merged growth layer is a multilayer structure in which uGaN layers and AlN layers or AlGaN layers are alternately stacked.
7. 7. The epitaxial wafer of claim 4, further comprising an Al (z) Ga (1-z) N stress control layer formed between the GaN-based merged growth layer and the GaN HEMT device active layer.
8. 8. The epitaxial wafer of claim 4, further comprising a second AlN nucleation layer formed between the plurality of SiOx protrusions and the GaN-based merged growth layer and covering exposed surfaces of the first AlN nucleation layer and surfaces of the SiOx protrusions.
9. 9. A method of fabricating an epitaxial wafer using a growth substrate wafer for a high performance GaN switching power device, the method comprising the steps of: (a) Preparing a Si (111) growth substrate; (b) Forming a first AlN nucleation layer on the Si (111) growth substrate; (c) Depositing a SiOx film on the first AlN nucleation layer; (d) Patterning the SiOx film to form a plurality of discontinuously spaced SiOx protrusions; (e) Forming a GaN-based merged growth layer by laterally growing (epitaxial lateral overgrowth, ELOG) a GaN-based material from the first AlN nucleation layer exposed between the SiOx protrusions and merging it over the SiOx protrusions, and (F) And stacking an active layer of the GaN HEMT device on the GaN-based combined growth layer.
10. 10. The method of claim 9, wherein the step (e) comprises forming a GaN-based combined growth layer by alternately and repeatedly growing a uGaN layer and one of an AlN layer and an AlGaN layer.
11. 11. The method of claim 9, further comprising the step of forming a second AlN nucleation layer on the first AlN nucleation layer and the plurality of SiOx protrusions between step (d) and step (e).

Description

Growth substrate wafer for high performance GaN switching power device, epitaxial wafer using the same, and method of manufacturing the same Technical Field The present invention relates to a high performance switching power device (SWITCHING POWER DEVICE) using gallium nitride (GaN), and more particularly, to a patterned silicon Substrate (PSiS, patterned Si Substrate) for forming a high quality GaN epitaxial layer on a silicon (Si) growth Substrate, and an epitaxial wafer and a method of manufacturing the same that significantly reduces threading dislocation density (THREADING DISLOCATION DENSITY, TDD) using the Substrate. Background Gallium nitride (GaN) compound semiconductors are a wide bandgap material that has a higher breakdown field, excellent thermal conductivity, and high carrier mobility compared to conventional semiconductor materials such as silicon (Si) and gallium arsenide (GaAs). Because of these characteristics, it can achieve high power density in a smaller size, and is attracting attention as a key material for next-generation power semiconductor devices. In order for GaN power semiconductors to be competitive in the market, normally-off operation with high blocking voltage and low leakage current is indispensable. The most desirable structure to achieve this is a vertical structure device (vertical FET) with thick epitaxial regions, but currently, a horizontal structure High Electron Mobility Transistor (HEMT) is mainly fabricated in which a thin film is grown on a hetero-growth substrate due to the difficulty of commercialization of GaN-on-GaN and inefficiency of ion implantation process. At this time, heterogeneous growth substrates such as sapphire, silicon (Si), and silicon carbide (SiC) are used, but very high Threading Dislocation Density (TDD) at a level of 10 7~1010/cm2 occurs due to lattice constant and thermal expansion coefficient mismatch between the GaN epitaxial layer and the growth substrate. These threading dislocations are a continuing problem that severely and adversely affect device performance and reliability. Specifically, threading dislocation causes various problems as follows. (1) Leakage current increases, threading dislocations (threading and mixed dislocations) containing a threading component act as the main leakage path, deteriorating the off-state characteristics of the device. (2) The blocking voltage decreases-threading dislocations act as "hot spots" which cause electric field crowding at specific points within the device, causing the device to prematurely break down before reaching its intrinsic breakdown voltage. (3) The switching frequency is reduced, threading dislocations act as scattering and trapping centers in the path of motion of the electrons, reducing carrier mobility. This performance degradation is particularly pronounced in horizontal HEMT structures where the current flows laterally to threading dislocations. (4) Dynamic on-Resistance (RON) increases, which is a phenomenon in which during high voltage switching operations, charge is trapped in defects, including threading dislocations, and then slowly released, causing an immediate temporary increase in on-resistance after switching on. This is a major cause of increased power loss. (5) The reliability is degraded in that crystal defects such as threading dislocation become the starting points of various degradation mechanisms such as gate edge degradation, hot electron generation, thin film delamination, etc. when the device is operated under high electric field and high temperature environments, thereby shortening the lifetime of the device. Therefore, in order to commercialize high-performance, high-reliability GaN power devices, development of a high-quality epitaxial growth technique capable of controlling TDD to less than 10 8/cm2 on a large-diameter 8-inch or 12-inch Si substrate is urgently required. Disclosure of Invention Technical problem The present invention has been designed to solve the problems of the prior art as described above, and its main object is to solve the high Threading Dislocation Density (TDD) problem occurring when a GaN epitaxial layer is grown on a large diameter silicon (Si) growth substrate. In particular, the present invention aims to greatly reduce TDD to less than 10 8/cm2 to provide a high quality GaN HEMT epitaxial wafer that can improve electrical characteristics such as leakage current, dynamic on-resistance, etc., enhancing breakdown voltage and reliability. Further, it is another object of the present invention to provide a growth substrate wafer for high performance GaN power devices and a method of manufacturing the same, which is suitable for 8-inch and 12-inch large diameter wafer processes, providing high productivity and cost effectiveness. Technical proposal There is provided, in accordance with an embodiment of the present invention, a growth substrate wafer for a high performance GaN switching power device, the growth substrate wafer inc