CN-122002872-A - Full-surrounding grid electrode field effect transistor and manufacturing method thereof

Abstract

The utility model relates to a full-surrounding grid electrode field effect transistor and a manufacturing method thereof, the full-surrounding grid electrode field effect transistor comprises a substrate, a grid electrode and a grid oxide layer, the substrate comprises a body and a silicon column which are connected with each other, the silicon column is arranged in a protruding mode, the silicon column comprises a conductive channel region and a source region and a drain region which are respectively formed on two sides of the conductive channel region, the conductive channel region is arranged between the source region and the drain region, a conductive channel is arranged in the conductive channel region, a dent or a bulge is formed on the outer surface of the conductive channel region, the grid electrode is arranged around the circumference of the conductive channel region and is attached to the outer wall of the conductive channel region, the grid oxide layer is arranged between the grid electrode and the conductive channel region in a surrounding mode, and the shape of the grid oxide layer is matched with the outer surface of the conductive channel region. By increasing the contact area between the grid electrode and the conductive channel region, the driving current capacity of the device can be improved, the contact resistance can be reduced, the voltage drop can be reduced, and the purposes of improving the switching speed and the working efficiency of the transistor can be achieved.

Inventors

• QIN YUTING

Assignees

• 成都新紫光半导体科技有限公司

Dates

Publication Date

20260508

Application Date

20241107

Claims (10)

1. 1. The full-surrounding grid electrode field effect transistor is characterized by comprising a substrate, a grid electrode and a grid oxide layer, wherein the substrate comprises a body and a silicon column which are connected with each other, and the silicon column is arranged protruding out of the body; The silicon column comprises a conductive channel region, a source region and a drain region, wherein the source region and the drain region are respectively formed at two sides of the conductive channel region, the conductive channel region is arranged between the source region and the drain region, and a conductive channel is arranged in the conductive channel region; the outer surface of the conductive channel region is formed with a recess or a protrusion; the grid electrode is arranged around the circumference of the conducting channel region and is attached to the outer wall of the conducting channel region; the gate oxide layer is circumferentially disposed between the gate and the conductive channel region, and the gate oxide layer matches the shape of the outer surface of the conductive channel region.
2. 2. The fully-around gate field effect transistor of claim 1, wherein the conductive channel region comprises a pillar portion and a ring portion, the ring portion being disposed around a circumference of the pillar portion.
3. 3. The fully-around gate field effect transistor of claim 2, wherein the number of the annular portions is plural, and the plurality of annular portions are arranged at intervals along the length direction of the silicon pillar.
4. 4. The fully-around gate field effect transistor of claim 2, wherein the pillar portion and the ring portion are integrally formed.
5. 5. The fully-around gate field effect transistor of any of claims 1-4 further comprising a first silicon dioxide layer deposited on a side of the gate adjacent to the body and a second silicon dioxide layer deposited on a side of the gate facing away from the body.
6. 6. A method for fabricating the fully-around gate field effect transistor of any of claims 1-5, comprising: Depositing the silicon column on the body, wherein the silicon column comprises a conductive channel region, a source region and a drain region which are respectively formed at two sides of the conductive channel region, and forming a concave or convex on the outer surface of the conductive channel region; depositing the gate oxide layer on an outer surface of the conductive channel region; And sequentially depositing a first silicon dioxide layer, a grid electrode and a second silicon dioxide layer along the length direction of the silicon column.
7. 7. The method of claim 6, wherein a first layer of silicon dioxide, a silicon nitride layer, and a second layer of silicon dioxide are deposited sequentially on the body prior to depositing the silicon pillars on the body; and performing photoetching and/or photo-etching operation, and forming a through hole penetrating through the first silicon dioxide layer, the silicon nitride layer and the second silicon dioxide layer in sequence, wherein the silicon column is deposited in the through hole.
8. 8. The method of claim 7, wherein the recessing or protruding an outer surface of the conductive channel region comprises: Etching back the silicon nitride layer in the through hole so that the inner diameter of the through hole formed on the silicon nitride layer is larger than that of the through holes formed on the first layer of silicon dioxide and the second layer of silicon dioxide; And depositing silicon seed crystals in the through holes, and epitaxially growing silicon to form the silicon columns.
9. 9. The method of claim 8, wherein the first layer of silicon dioxide, the silicon nitride layer, and the second layer of silicon dioxide are removed, and a replacement gate oxide is deposited on the periphery of the conductive channel region, the source region, and doping is performed on the drain region, and after doping is completed, the replacement gate oxide is removed.
10. 10. The method of claim 6, wherein after depositing the first silicon dioxide layer along the length of the silicon pillars, depositing the gate oxide layer on the outer surfaces of the silicon pillars above the first silicon dioxide layer; after depositing the grid electrode above the first silicon dioxide layer along the length direction of the silicon column, removing and doping the grid oxide layer above the grid electrode; A second silicon dioxide layer is deposited over the gate along the length of the silicon pillars.

Description

Full-surrounding grid electrode field effect transistor and manufacturing method thereof Technical Field The present disclosure relates to the field of field effect transistors, and in particular, to a full-surrounding gate field effect transistor and a method for manufacturing the same. Background With the continuous progress of semiconductor process technology, planar transistors are gradually upgraded to Gate All Around (GAA) field effect transistors, which improves the control of the conduction channel by completely surrounding the conduction channel under the Gate. However, the conventional full-surrounding gate field effect transistor still has a disadvantage in gate control, resulting in limited device performance. Disclosure of Invention The disclosure provides a full-surrounding gate field effect transistor and a manufacturing method thereof, which are used for solving the technical problems in the related art. In order to achieve the above object, a first aspect of the present disclosure provides a full-surrounding gate field effect transistor, including a substrate, a gate, and a gate oxide layer, the substrate including a body and a silicon pillar connected to each other, the silicon pillar protruding from the body; The silicon column comprises a conductive channel region, a source region and a drain region, wherein the source region and the drain region are respectively formed at two sides of the conductive channel region, the conductive channel region is arranged between the source region and the drain region, and a conductive channel is arranged in the conductive channel region; the outer surface of the conductive channel region is formed with a recess or a protrusion; the grid electrode is arranged around the circumference of the conducting channel region and is attached to the outer wall of the conducting channel region; the gate oxide layer is circumferentially disposed between the gate and the conductive channel region, and the gate oxide layer matches the shape of the outer surface of the conductive channel region. Optionally, the conductive channel region includes a columnar portion and an annular portion disposed around a circumference of the columnar portion. Optionally, the plurality of annular parts are arranged at intervals along the length direction of the silicon column. Optionally, the columnar portion and the annular portion are configured as an integral molding. Optionally, the fully-surrounding gate field effect transistor further comprises a first silicon dioxide layer and a second silicon dioxide layer, wherein the first silicon dioxide layer is deposited on one side of the gate close to the body, and the second silicon dioxide layer is deposited on one side of the gate away from the body. A second aspect of the present disclosure provides a method for fabricating a fully-around gate field effect transistor as described above, comprising: Depositing the silicon column on the body, wherein the silicon column comprises a conductive channel region, a source region and a drain region which are respectively formed at two sides of the conductive channel region, and forming a concave or convex on the outer surface of the conductive channel region; depositing the gate oxide layer on an outer surface of the conductive channel region; And sequentially depositing a first silicon dioxide layer, a grid electrode and a second silicon dioxide layer along the length direction of the silicon column. Optionally, depositing a first layer of silicon dioxide, a silicon nitride layer and a second layer of silicon dioxide on the body in sequence before depositing the silicon pillars on the body; and performing photoetching and/or photo-etching operation, and forming a through hole penetrating through the first silicon dioxide layer, the silicon nitride layer and the second silicon dioxide layer in sequence, wherein the silicon column is deposited in the through hole. Optionally, the forming the recess or the protrusion on the outer surface of the conductive channel region includes: Etching back the silicon nitride layer in the through hole so that the inner diameter of the through hole formed on the silicon nitride layer is larger than that of the through holes formed on the first silicon dioxide layer and the second silicon dioxide layer; And depositing silicon seed crystals in the through holes, and epitaxially growing silicon to form the silicon columns. Optionally, removing the first silicon dioxide layer, the silicon nitride layer and the second silicon dioxide layer, depositing a replacement gate oxide on the peripheries of the conductive channel region and the source region, doping the drain region, and removing the replacement gate oxide after doping is completed. Optionally, after the first silicon dioxide layer is deposited along the length direction of the silicon column, depositing the gate oxide layer on the outer surface of the silicon column above the first silicon dioxide layer; a