CN-122002876-A - Submicron gate etching method based on etching compensation and power modulation

CN122002876ACN 122002876 ACN122002876 ACN 122002876ACN-122002876-A

Abstract

The invention relates to a submicron gate etching method based on etching compensation and power modulation, which comprises the steps of providing a sample wafer, patterning the photoresist in a gate region to form a photoresist line, etching the passivation dielectric layer in the gate region to the inside of the passivation dielectric layer by using the photoresist line under a first etching parameter, and continuing to etch the passivation dielectric layer in the gate region under a second etching parameter until a submicron gate groove is formed by etching, wherein the initial line width of the photoresist line is smaller than the length of a target gate, and the etching power in the second etching parameter is smaller than the etching power in the first etching parameter. The method effectively controls the actual size of the submicron grid, realizes the accurate control of the submicron grid size, has little damage to the barrier layer, has high pattern fidelity, and synchronously achieves high precision and low damage.

Inventors

ZHOU YUWEI
WEN SIQI
Fu Minhan
Gong can
MA XIAOHUA
HAO YUE

Assignees

西安电子科技大学

Dates

Publication Date: 20260508
Application Date: 20260130

Claims (9)

1. The submicron gate etching method based on etching compensation and power modulation is characterized by comprising the following steps: providing a sample wafer, wherein the sample wafer comprises a passivation dielectric layer and photoresist positioned on the passivation dielectric layer; patterning the photoresist in the gate region to form a photoresist line, wherein the initial line width of the photoresist line is smaller than the length of the target gate; Under a first etching parameter, etching the passivation dielectric layer of the gate region by using the photoresist line in a first stage until the passivation dielectric layer is etched; And continuing to etch the passivation dielectric layer of the gate region in a second stage under a second etching parameter until a submicron gate groove is formed by etching, wherein the etching power in the second etching parameter is smaller than that in the first etching parameter, and the length of the gate groove is equal to that of the target gate.
2. The submicron gate etching method based on etching compensation and power modulation according to claim 1, wherein the sample wafer further comprises a substrate and a heterojunction structure, and the heterojunction structure, the passivation dielectric layer and the photoresist are sequentially laminated on the substrate.
3. The submicron gate etching method based on etching compensation and power modulation according to claim 1, wherein the method for determining the initial line width of the photoresist line is as follows: Providing an experimental sample wafer, wherein the experimental sample wafer comprises an experimental passivation dielectric layer and an experimental photoresist positioned on the experimental passivation dielectric layer; exposing experimental photoresist by using an electron beam lithography machine to form a photoresist line group, wherein a plurality of lines in the photoresist line group have different line widths and have line widths smaller than, larger than and equal to those of a target grid; Etching the experimental passivation dielectric layer by using the photoresist line group under the first etching parameter, and forming a plurality of etching lines in the experimental passivation dielectric layer under the same etching target depth and the same etching time; And measuring the actual widths of the etched lines, and selecting the line width of the photoresist line with the width identical to the length of the target grid as the initial line width.
4. The submicron gate etching method based on etching compensation and power modulation according to claim 1, wherein the length of the target gate is 95-105nm, and the initial line width is 70-80nm.
5. The submicron gate etching method based on etching compensation and power modulation according to claim 1, characterized in that the etching power in the first etching parameter is 200-1000W.
6. The method of claim 5, wherein the first etching parameters include an upper electrode power of 250W, a lower electrode power of 40W, a CF 4 gas flow of 50sccm, and a chamber pressure of 5mT.
7. The submicron gate etching method based on etching compensation and power modulation according to claim 1, characterized in that the etching power in the second etching parameter is 50-100W.
8. The method of claim 7, wherein the second etching parameters include an upper electrode power of 80W, a lower electrode power of 10W, a CF 4 gas flow of 50sccm, and a chamber pressure of 5mT.
9. The submicron gate etching method based on etching compensation and power modulation according to claim 1, characterized in that the depth ratio of the first stage etching to the second stage etching is 9:1.

Description

Submicron gate etching method based on etching compensation and power modulation Technical Field The invention belongs to the technical field of semiconductor processes, and particularly relates to a submicron gate etching method based on etching compensation and power modulation. Background With the rapid development of the fifth generation (5G) and future wireless communication technologies to millimeter wave frequency bands (such as Ka-band and Q-band), the performance requirements on core radio frequency power devices are increasingly severe. Gallium nitride high electron mobility transistors (GaN HEMTs) are the core of millimeter wave band high power devices because of their excellent wide bandgap characteristics, such as high breakdown field, high electron saturation velocity, and excellent thermal stability. The frequency characteristics of the device are closely related to the gate length, and the shorter the gate length is, the higher the cut-off frequency is. Therefore, realizing sub-micron gates of 0.1 micron and below is a key technology for millimeter wave GaN devices. There are a large number of surface states, such as dangling bonds, defects, etc., on GaN and AlGaN surfaces. When the device is operated in a high voltage (high drain voltage) switch state, electrons in a channel can be captured by the surface states to form a virtual grid, so that two-dimensional electron gas (2 DEG) below the virtual grid is exhausted, the on-resistance is increased sharply, and the output current is reduced, namely the current collapses. The passivation dielectric layer of silicon nitride (SiN) passivates dangling bonds on the GaN surface through chemical bonds (mainly Si-N bonds), and the surface state density is obviously reduced. The electron is prevented from being captured by the surface state, so that the current collapse phenomenon is greatly relieved, and the dynamic performance and the output power of the device under high-frequency and high-power switches are ensured. Based on the passivation scheme, the passivation dielectric layer is required to be etched to prepare the gate groove, so that necessary conditions are provided for the subsequent preparation of gate metal. Currently, the etching schemes for forming the gate trench mainly include the following two methods: In the first scheme, an F-based plasma etching process with fixed parameters is adopted. The scheme generally sets a set of parameters such as fixed radio frequency source power, radio frequency bias power, chamber pressure, gas flow and the like, and performs a one-time etching process. For example, higher bias power (e.g., above 200 watts) is used to ensure etch verticality, which can exacerbate plasma damage, or lower power is used to mitigate damage, which can result in problems of too slow etch rate, poor anisotropy, poor sidewall topography, etc. In a second scheme, atomic Layer Etching (ALE) is used. Atomic-scale precision etching and extremely low damage are achieved by self-limiting surface reactions, such as modification-removal cycles. ALE is considered as an ultimate solution for realizing ultra-low damage and nano-scale precision gate recess etching, but faces the challenges of complex process, high equipment requirements and slow etching rate. However, the existing etching scheme has the defects that the difference between the size of a photoetching line and the size of a final grid electrode is large due to obvious transverse etching of fixed low-power etching, accurate pattern transfer of a submicron grid electrode cannot be realized, the size control is inaccurate, high-energy ions continuously bombard the bottom of the grid electrode, irreversible damage is caused to an underlying AlGaN barrier layer and a two-dimensional electron gas channel, the performance of a device is deteriorated, a single parameter set is required to be accurately optimized for balancing the etching rate and the damage, the process tolerance is small, the repeatability and the stability are poor, the ALE etching rate is slow, the damage can be lower, but the etching of a passivation dielectric layer is high in time cost, and the process efficiency is low. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a submicron gate etching method based on etching compensation and power modulation. The technical problems to be solved by the invention are realized by the following technical scheme: the embodiment of the invention provides a submicron gate etching method based on etching compensation and power modulation, which comprises the following steps: providing a sample wafer, wherein the sample wafer comprises a passivation dielectric layer and photoresist positioned on the passivation dielectric layer; patterning the photoresist in the gate region to form a photoresist line, wherein the initial line width of the photoresist line is smaller than the length of the target gate; Under a first etching para