CN-122002877-A - Gate structure and manufacturing method thereof

Abstract

The invention provides a gate structure and a manufacturing method thereof. The gate structure includes a gate assembly, a first spacer, a cap layer, a hard mask layer, and a second spacer. The gate assembly is disposed on a substrate. The first spacer is disposed on a sidewall of the gate assembly. The top cover layer is arranged on the top surface of the grid assembly. The hard mask layer is disposed on the cap layer. The second spacer is disposed on a sidewall of the hard mask layer, a sidewall of the cap layer, and a sidewall of the first spacer.

Inventors

• XU BOYAN
• CAI SHINING
• CAO YUJIA
• WU BOLUN

Assignees

• 华邦电子股份有限公司

Dates

Publication Date

20260508

Application Date

20241205

Priority Date

20241104

Claims (20)

1. 1. A gate structure, comprising: a gate assembly disposed on the substrate; A first spacer disposed on a sidewall of the gate assembly; A capping layer disposed on a top surface of the gate assembly; A hard mask layer disposed on the cap layer, and And a second spacer disposed on a sidewall of the hard mask layer, a sidewall of the cap layer, and the first spacer.
2. 2. The gate structure of claim 1, wherein a top surface of the second spacer and a top surface of the hard mask layer are coplanar.
3. 3. The gate structure of claim 1, wherein a material of the first spacer is different from a material of the second spacer.
4. 4. The gate structure of claim 1, wherein a material of the cap layer is different from a material of the second spacer.
5. 5. The gate structure of claim 1, wherein a material of the hard mask layer is the same as a material of the second spacer.
6. 6. The gate structure of claim 1, wherein the hard mask layer comprises a first sub-hard mask layer and a second sub-hard mask layer, and the second sub-hard mask layer is disposed in the first sub-hard mask layer.
7. 7. The gate structure of claim 6, wherein a top surface of the second spacer, a top surface of the first sub-hard mask layer, and a top surface of the second sub-hard mask layer are coplanar.
8. 8. The gate structure of claim 6, wherein a material of the first sub-hard mask layer is different from a material of the second sub-hard mask layer, and the first sub-hard mask layer and the second spacer comprise the same material.
9. 9. The gate structure of claim 6, wherein an interface between a sidewall of the second sub-hard mask layer and the first sub-hard mask layer is planar.
10. 10. The gate structure of claim 6, wherein an interface between a sidewall of the second sub-hard mask layer and the first sub-hard mask layer is curved.
11. 11. The gate structure of claim 1, wherein the gate assembly comprises a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate disposed sequentially on the substrate.
12. 12. A method of fabricating a gate structure, comprising: sequentially forming a gate assembly, a top cover layer and a hard mask layer on a substrate; Forming a first spacer on the sidewall of the gate assembly, and Second spacers are formed on sidewalls of the hard mask layer, on sidewalls of the cap layer, and on the first spacers.
13. 13. The method of claim 12, wherein a top surface of the second spacer and a top surface of the hard mask layer are coplanar.
14. 14. The method of manufacturing a gate structure according to claim 12, further comprising, after forming the second spacer: forming a sacrificial layer on the substrate, wherein the sacrificial layer covers the second spacer and the hard mask layer; removing a portion of the sacrificial layer until a top surface of the hard mask layer is exposed; Removing the hard mask layer to form a groove; conformally forming a first mask material layer on the sacrificial layer and the recess; forming a second mask material layer on the first mask material layer, wherein the second mask material layer fills the grooves, and And removing the first mask material layer and the second mask material layer outside the groove to form a first sub-hard mask layer and a second sub-hard mask layer in the groove, wherein the first sub-hard mask layer is positioned between the second sub-hard mask layer and the side wall and the bottom surface of the groove.
15. 15. The method of claim 14, wherein a top surface of the second spacer, a top surface of the first sub-hard mask layer, and a top surface of the second sub-hard mask layer are coplanar.
16. 16. The method of claim 14, wherein an interface between a sidewall of the second sub-hard mask layer and the first sub-hard mask layer is planar.
17. 17. The method of manufacturing a gate structure according to claim 12, further comprising, after forming the second spacer: forming a sacrificial layer on the substrate, wherein the sacrificial layer covers the second spacer and the hard mask layer; removing a portion of the sacrificial layer until a top surface of the hard mask layer is exposed; removing a portion of the hard mask layer to form a first sub-hard mask layer having a recess, and And forming a second sub hard mask layer in the groove.
18. 18. The method of claim 17, wherein removing a portion of the hard mask layer comprises performing an anisotropic etching process.
19. 19. The method of claim 17, wherein an interface between a sidewall of the second sub-hard mask layer and the first sub-hard mask layer is curved.
20. 20. The method of claim 12, wherein the gate assembly comprises a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially formed on the substrate.

Description

Gate structure and manufacturing method thereof Technical Field The invention relates to a gate structure and a manufacturing method thereof. Background Generally, after forming a memory cell of a flash memory, spacers are formed on sidewalls of the memory cell. Thereafter, in order to increase the data retention capability, a mask material layer is formed on the memory cells and the spacers, and the mask material layer is patterned to form a mask pattern connected to the spacers on the memory cells. However, if the position of the mask pattern is shifted, a portion of the top surface of the memory cell is exposed. In this way, contaminants (e.g., metal ions) in the subsequent process may enter the memory cell, which may affect device performance and reliability. In addition, during the planarization process after the formation of the mask material layer, the top surface of the mask material layer is easily recessed (dishing), so that the spacers of the memory cells cannot be well protected, and the spacers of the memory cells may be damaged in the subsequent process. As such, a problem of word line leakage may occur during testing or operation of the flash memory. Disclosure of Invention The invention aims at a grid structure and a manufacturing method thereof, which can solve the problem that a mask pattern cannot well protect a memory cell or a spacer of the memory cell. The gate structure of the present invention includes a gate assembly, a first spacer, a cap layer, a hard mask layer, and a second spacer. The gate assembly is disposed on a substrate. The first spacer is disposed on a sidewall of the gate assembly. The top cover layer is arranged on the top surface of the grid assembly. The hard mask layer is disposed on the cap layer. The second spacer is disposed on a sidewall of the hard mask layer, a sidewall of the cap layer, and a sidewall of the first spacer. The manufacturing method of the gate structure comprises the following steps. A gate assembly, a cap layer, and a hard mask layer are sequentially formed on a substrate. A first spacer is formed on a sidewall of the gate assembly. And forming second spacers on the sidewalls of the hard mask layer, the sidewalls of the cap layer and the sidewalls of the first spacers. In view of the above, in the gate structure of the present invention, the hard mask layer is disposed on the cap layer and the second spacers are disposed on the sidewalls of the hard mask layer and the cap layer and on the first spacers, so that the cap layer can be protected by the hard mask layer and the second spacers, and the first spacers can also be protected by the second spacers. In this way, contaminants (e.g., metal ions) can be effectively prevented from entering the gate assembly through the cap layer or the first spacer in the subsequent process, and the spacers of the memory cell can be well protected. Drawings Fig. 1A to 1C are schematic cross-sectional views illustrating a manufacturing process of a gate structure according to a first embodiment of the present invention; fig. 2A to 2D are schematic cross-sectional views illustrating a manufacturing process of a gate structure according to a second embodiment of the present invention; fig. 3A to 3C are schematic cross-sectional views illustrating a manufacturing process of a gate structure according to a third embodiment of the present invention. Detailed Description In the following description, when an element is described as being disposed "on" another element, the element may be in direct contact with the other element, or other elements may be present therebetween. In the following embodiments, when the gate structure is part of a flash memory (e.g., a NOR flash memory), the gate elements may include a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially disposed on a substrate, but the present invention is not limited thereto. The manufacturing flow of the gate structure according to the first embodiment of the present invention will be described below with reference to fig. 1A to 1C. Referring to fig. 1A, a dielectric layer 102, a conductive layer 104, a dielectric layer 106, a conductive layer 108, a dielectric layer 110, and a dielectric layer 112 are sequentially formed on a substrate 100. In the present embodiment, the substrate 100 is, for example, a silicon substrate or a silicon on insulator, but the present invention is not limited thereto. The dielectric layer 102 is, for example, an oxide layer, which may be formed by, for example, a thermal oxidation process or a chemical vapor deposition process. Dielectric layer 102 may be used to form a tunnel dielectric layer for a gate structure. The conductive layers 104, 108 are, for example, polysilicon layers, wherein the conductive layer 104 may be used to form a floating gate of a gate structure and the conductive layer 108 may be used to form a control gate of the gate structure. Dielectric layer 1