CN-122002878-A - Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device having improved Gate Induced Drain Leakage (GIDL) and a method of manufacturing the same are provided. The semiconductor device includes a trench formed in a substrate, a first gate dielectric layer adapted to cover a bottom surface and sidewalls of the trench, a first buried conductive layer adapted to fill a bottom of the trench over the first gate dielectric layer, a second buried conductive layer including a conductive metal oxide and over the first buried conductive layer, and a second gate dielectric layer disposed between the second buried conductive layer and the first gate dielectric layer.

Inventors

• HUANG SHENGHUAN

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260508

Application Date

20250801

Priority Date

20241104

Claims (11)

1. 1. A semiconductor device, comprising: A trench formed in the substrate; a first gate dielectric layer covering bottom surfaces and sidewalls of the trench; a first buried conductive layer filling a bottom of the trench over the first gate dielectric layer; A second buried conductive layer comprising a conductive metal oxide over the first buried conductive layer, and A second gate dielectric layer disposed between the second buried conductive layer and the first gate dielectric layer.
2. 2. The semiconductor device of claim 1, wherein the first buried conductive layer comprises a metal or a metal nitride.
3. 3. The semiconductor device of claim 1, wherein the second buried conductive layer comprises a stacked structure of a conductive metal oxide, a metal nitride, and polysilicon, or a stacked structure of a conductive metal oxide, a metal, and polysilicon.
4. 4. The semiconductor device of claim 1, wherein the conductive metal oxide comprises the same metal as the first buried conductive layer.
5. 5. The semiconductor device of claim 1, wherein the first buried conductive layer comprises titanium nitride.
6. 6. The semiconductor device of claim 1, wherein the conductive metal oxide comprises titanium oxide.
7. 7. The semiconductor device of claim 1, wherein the second gate dielectric layer comprises silicon oxide.
8. 8. The semiconductor device of claim 1, further comprising: a fin region under the first buried conductive layer, Wherein the upper surface and sidewalls of the fin region are covered by the first gate dielectric layer.
9. 9. The semiconductor device of claim 1, further comprising a gate cap layer adapted to fill a remaining portion of the trench over the second buried conductive layer.
10. 10. The semiconductor device of claim 1, further comprising first and second conductive regions in the substrate on either side of the trench.
11. 11. The semiconductor device of claim 1, wherein the substrate comprises a plurality of active regions spaced apart from one another, and Wherein the trenches are disposed in each of the active regions.

Description

Semiconductor device and method of manufacturing the same Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2024-0154258 filed on 4-11-2024, which is incorporated herein by reference in its entirety. Technical Field Embodiments of the present invention relate generally to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including buried gates and a method of manufacturing the semiconductor device. Background The metal gate electrode is used to realize a high performance transistor. For buried gate transistors, it is critical to control the threshold voltage to obtain optimal performance. In addition, gate Induced Drain Leakage (GIDL) characteristics significantly affect the performance of these transistors. However, as semiconductor devices become more integrated, improving GIDL characteristics becomes more and more challenging. Disclosure of Invention Embodiments of the present disclosure relate to a semiconductor device having improved Gate Induced Drain Leakage (GIDL) and a method of manufacturing the semiconductor device. According to an embodiment of the present disclosure, a semiconductor device includes a trench formed in a substrate, a first gate dielectric layer adapted to cover a bottom surface and sidewalls of the trench, a first buried conductive layer adapted to fill a bottom of the trench over the first gate dielectric layer, a second buried conductive layer over the first buried conductive layer and including a conductive metal oxide, and a second gate dielectric layer disposed between the second buried conductive layer and the first gate dielectric layer. According to another embodiment of the present disclosure, a method for fabricating a semiconductor device includes forming a trench in a substrate, forming a first gate dielectric layer adapted to cover a bottom surface and sidewalls of the trench, forming a first buried conductive layer over the first gate dielectric layer adapted to fill a bottom of the trench, forming a dielectric oxide layer over the first buried conductive layer and the first gate dielectric layer, forming a second buried conductive layer over the dielectric oxide layer, and performing an annealing process to replace the dielectric oxide layer between the first buried conductive layer and the second buried conductive layer with a conductive metal oxide and form the dielectric oxide layer between the first gate dielectric layer and the second buried conductive layer as a second gate dielectric layer. According to another embodiment of the present disclosure, a semiconductor device includes a trench formed in a substrate, a first gate dielectric layer adapted to cover a bottom surface and sidewalls of the trench, a buried conductive layer including a conductive metal oxide in an upper portion of the first gate dielectric layer, and a second gate dielectric layer adapted to cover a portion of the first gate dielectric layer between the buried conductive layer and the first gate dielectric layer. According to another embodiment of the present disclosure, a semiconductor device includes a trench formed in a substrate, a first gate dielectric layer adapted to cover a bottom surface and sidewalls of the trench, a first buried conductive layer adapted to fill a bottom of the trench over the first gate dielectric layer, a conductive metal oxide electrode disposed on an upper portion of the first buried conductive layer, wherein a line width of a bottom surface of the conductive metal oxide is wider than a line width of a top surface, a second buried conductive layer disposed on an upper portion of the metal oxide electrode, and a second gate dielectric layer disposed between the metal oxide electrode and the second buried conductive layer and the first gate dielectric layer. These and other features and advantages of the embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description, taken in conjunction with the accompanying drawings. Drawings Fig. 1A is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Fig. 1B and 1C are cross-sectional views illustrating a semiconductor device according to an embodiment of the present disclosure. Fig. 2A to 2G are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 3A to 3G are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure. Fig. 4A to 4H are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to still another embodiment of the present disclosure. Fig. 5A is a plan view illustrating a semiconductor device according to another embodiment of the pres