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CN-122002879-A - Multi-suspension shielding grid MOSFET and preparation method thereof

CN122002879ACN 122002879 ACN122002879 ACN 122002879ACN-122002879-A

Abstract

The application provides a multi-suspension shielding grid MOSFET and a preparation method thereof, wherein the shielding grid is divided into a left part, a middle part and a right part, the left and right portions are symmetrically distributed along a middle portion, an upper width of the middle portion is greater than a lower width, and a top of the middle portion is higher than a top of the left and right portions. The middle part of the shielding grid is connected with the source electrode, the left part and the right part of the shielding grid float, the left part and the right part float, under the blocking state, the electric field distribution in the middle part of the drift region can be improved, the thicker field oxide layer at the bottom can bear higher electric field, the breakdown of a device is avoided to occur at the bottom of the shielding grid electrode, the reliability is improved, the output capacitance Coss contributed by the shielding grid electrode is reduced, the switching loss is reduced, and in addition, the shielding grid has lower on-resistance when the withstand voltage is the same.

Inventors

  • GENG JUNJIE
  • SHI LEI
  • LIU SHASHA

Assignees

  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260508
Application Date
20260127

Claims (13)

  1. 1. A multi-suspension shielding grid MOSFET is characterized by comprising a substrate, a buffer layer and an epitaxial layer which are stacked from bottom to top, wherein the shielding grid formed in the epitaxial layer is divided into a left part, a middle part and a right part, the left part and the right part are symmetrically distributed along a middle part, the upper width of the middle part is larger than the lower width, the top of the middle part is higher than the top of the left part and the right part, the grid positioned above the shielding grid in the epitaxial layer is formed, the middle part of the shielding grid is connected with a source electrode, and the left part and the right part float.
  2. 2. A method for preparing a multi-suspension shielded gate MOSFET, the method comprising: Providing a substrate, sequentially forming a buffer layer and an epitaxial layer on the substrate, forming a groove in the epitaxial layer, and sequentially forming a first oxide layer and a sacrificial material layer in the groove; Step two, etching the sacrificial material layer and the first oxide layer in sequence; Step three, after the sacrificial material layer is removed, a second oxide layer and a first grid material layer are sequentially formed in the groove; grinding the first grid electrode material layer until the second oxide layer is exposed; step five, etching the first grid material layer to enable the thickness of the upper portion of the first grid material layer to reach a preset value; step six, forming a third oxide layer in the groove; Step seven, etching the third oxide layer until the top of the first grid electrode material layer is exposed; step eight, removing the exposed first grid material layer to form left and right parts of the shielding grid; Step nine, forming a fourth oxide layer in the groove; forming a second grid material layer in the groove to form the middle part of the shielding grid; step eleven, forming a fifth oxide layer in the groove to cover the top of the second grid material layer; and twelve, sequentially forming a gate dielectric layer and a third gate material layer in the groove.
  3. 3. The method of claim 2, wherein the material of the sacrificial material layer comprises an anti-reflective coating.
  4. 4. The method of claim 2, wherein after the second step, the top of the sacrificial material layer is higher than the top of the first oxide layer.
  5. 5. The method of claim 2, wherein forming the second oxide layer comprises forming a second oxide layer within the trench by a deposition process overlying the first oxide layer, and performing an annealing process to densify the formed oxide layer.
  6. 6. The method of claim 2, wherein after forming the third oxide layer, a width of the trench opening is greater than a top width of a lower portion of the first gate material layer.
  7. 7. The method according to claim 2 or 6, wherein the third oxide layer is composed of an oxide layer formed by a thermal oxidation process and an oxide layer formed by a deposition process.
  8. 8. The method of claim 2, wherein a top corner of the third oxide layer is rounded after the end of step seven.
  9. 9. The method of claim 2, wherein the removing is performed by a sidewall barrier etch process in step eight.
  10. 10. The method of claim 2 wherein after forming the fourth oxide layer, the width of the upper gap in the trench is greater than the width of the lower gap, the left and right portions of the shield gate comprising a floating shield gate.
  11. 11. The method according to claim 2 or 10, characterized in that the fourth oxide layer consists of an oxide layer formed by a thermal oxidation process and of an oxide layer formed by a deposition process.
  12. 12. The method of claim 2 wherein forming the fifth oxide layer in the trench comprises forming the fifth oxide layer by a high aspect ratio deposition process, covering the fourth oxide layer while filling the trench, removing the oxide layer outside the trench by a grinding process, and etching the oxide layer in the trench to expose a portion of the sidewalls of the trench but not to expose the top of the second gate material layer.
  13. 13. The method of claim 2, further comprising performing a well implant after forming the third gate material layer in the trench, forming an interlayer dielectric layer, forming a contact hole, performing a contact hole implant, filling a metal contact plug in the contact hole, forming a source electrode and a gate electrode, and connecting through the metal contact plug.

Description

Multi-suspension shielding grid MOSFET and preparation method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a multi-suspension shielding grid MOSFET and a preparation method thereof. Background The shielding grid MOSFET (SGT MOSFET) improves the power figure of merit and reduces the grid drain capacitance and the switching loss by introducing an electrode separated from the grid. With the increasing market demand for power MOS in recent years, it is very important to realize a device with high breakdown voltage and low on-resistance. However, there is a contradictory relationship between the on-Resistance (RDSON) and the Breakdown Voltage (BVDSS), the on-resistance mainly consists of R CH + RD + RSUB, and as the breakdown voltage increases, R D increases significantly. Therefore, it is necessary to further reduce the on-resistance of the device while increasing the breakdown voltage of the shielded gate MOSFET to improve the performance and competitiveness of the device. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a multi-floating shielded gate MOSFET and a method for manufacturing the same, which are used for solving the problem that the breakdown voltage of the shielded gate MOSFET is increased and the on-resistance is increased obviously in the prior art. To achieve the above and other related objects, the present application provides a multi-floating shield gate MOSFET and a method of manufacturing the same. The technical scheme is as follows: In a first aspect, an embodiment of the application provides a multi-suspension shielded gate MOSFET, which comprises a substrate, a buffer layer and an epitaxial layer which are stacked from bottom to top, wherein the shielded gate formed in the epitaxial layer is divided into a left part, a middle part and a right part, the left part and the right part are symmetrically distributed along the middle part, the upper width of the middle part is larger than the lower width, the top of the middle part is higher than the top of the left part and the right part, the grid is formed above the shielded gate in the epitaxial layer, the middle part of the shielded gate is connected with a source electrode, and the left part and the right part float. In a second aspect, an embodiment of the present application provides a method for preparing a multi-suspension shielded gate MOSFET, including: providing a substrate, sequentially forming a buffer layer and an epitaxial layer on the substrate, forming a groove in the epitaxial layer, and sequentially forming a first oxide layer and a sacrificial material layer in the groove; step two, etching the sacrificial material layer and the first oxide layer in sequence; Step three, after the sacrificial material layer is removed, a second oxide layer and a first grid material layer are sequentially formed in the groove; Grinding the first grid material layer until the second oxide layer is exposed; step five, etching the first grid material layer to enable the thickness of the upper portion of the first grid material layer to reach a preset value; step six, forming a third oxide layer in the groove; Step seven, etching the third oxide layer until the top of the first grid electrode material layer is exposed; Step eight, removing the exposed first grid material layer to form left and right parts of the shielding grid; Step nine, forming a fourth oxide layer in the groove; Forming a second grid material layer in the groove to form the middle part of the shielding grid; Step eleven, forming a fifth oxide layer in the groove to cover the top of the second grid material layer; And twelve, sequentially forming a gate dielectric layer and a third gate material layer in the groove. Preferably, the material of the sacrificial material layer comprises an anti-reflective coating. Preferably, after the second step is finished, the top of the sacrificial material layer is higher than the top of the first oxide layer. Preferably, the step of forming the second oxide layer includes forming the second oxide layer in the trench to cover the first oxide layer by a deposition process, and performing an annealing process to densify the formed oxide layer. Preferably, after the third oxide layer is formed, the width of the trench opening is greater than the top width of the lower portion of the first gate material layer. Preferably, the third oxide layer is composed of an oxide layer formed by a thermal oxidation process and an oxide layer formed by a deposition process. Preferably, after the step seven is finished, the top corner of the third oxide layer is rounded. Preferably, in the eighth step, the removing is performed by a sidewall barrier etching process. Preferably, after the fourth oxide layer is formed, the width of the upper gap in the trench is larger than that of the lower gap, and the left and r