CN-122002881-A - Silicon carbide MOSFET with integrated polysilicon silicon carbide heterojunction diode

Abstract

The present disclosure relates to silicon carbide MOSFETs with integrated polysilicon silicon carbide heterojunction diodes. A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate may have an upper surface and a bottom surface. The semiconductor substrate may be made of polycrystalline silicon carbide. The semiconductor structure may further include a drift region of the first conductivity type on an upper surface of the semiconductor substrate. The semiconductor structure may further include a first region of the upper surface of the semiconductor substrate including a formation region of the transistor and a second region of the upper surface of the semiconductor substrate adjacent to the first region and including a formation region of the schottky barrier diode.

Inventors

• LI MENGJIA
• D. M. Lisbud

Assignees

• 瑞萨电子株式会社

Dates

Publication Date

20260508

Application Date

20250930

Priority Date

20241105

Claims (20)

1. 1. A semiconductor structure, comprising: A semiconductor substrate of a first conductivity type having an upper surface and a bottom surface, the semiconductor substrate comprising polycrystalline silicon carbide; A drift region of the first conductivity type on the upper surface of the semiconductor substrate; a first region of the upper surface of the semiconductor substrate including a transistor formation region, and A second region of the upper surface of the semiconductor substrate, adjacent to the first region, includes a schottky barrier diode formation region.
2. 2. The semiconductor structure of claim 1, wherein the first region comprises: A pair of channel regions of a second conductivity type, the pair of channel regions being located within the drift region, the second conductivity type being opposite to the first conductivity type; A pair of source regions of the first conductivity type disposed over and in contact with the pair of channel regions, and A gate electrode disposed over the first portion of the oxide layer, wherein the pair of source regions are adjacent to the gate electrode.
3. 3. The semiconductor structure of claim 2, wherein the second region adjacent to the first region comprises: A polysilicon layer within the trench over the drift region, the polysilicon layer providing a schottky electrode; A second portion of the oxide layer disposed on opposite vertical sidewalls of the polysilicon layer, the second portion of the oxide layer having a gap on a bottom surface of the polysilicon layer, and A second semiconductor region of a second conductivity type within the drift region, wherein the gap in the second portion of the oxide layer allows the bottom surface of the polysilicon layer to contact the second semiconductor region to provide a polysilicon/SiC heterojunction diode.
4. 4. The semiconductor structure of claim 3 wherein the schottky electrode and the second semiconductor region are electrically connected at a bottom portion of the trench.
5. 5. The semiconductor structure of claim 4 wherein the schottky electrode and the second semiconductor region provide a schottky barrier rectifier located at the bottom portion of the trench.
6. 6. The semiconductor structure of claim 3 wherein the schottky electrode and the pair of source regions are electrically connected to a source terminal.
7. 7. The semiconductor structure of claim 3 wherein the schottky electrode comprises the polysilicon carbide layer.
8. 8. The semiconductor structure of claim 4, wherein a depth of the second semiconductor region within the drift region from the bottom portion of the trench varies between 0.1um and 5 um.
9. 9. The semiconductor structure of claim 3, wherein a dopant concentration of the second semiconductor region is greater than 1 x 10 17 cm -3 and less than 1 x 10 20 cm -3 .
10. 10. The semiconductor structure of claim 3, wherein the trench and the pair of source regions are separated by a predetermined distance that varies between 0um and 5 um.
11. 11. The semiconductor structure of claim 3, further comprising: A first semiconductor region located between at least one of the pair of source regions and the trench, and And a drain terminal disposed on a bottom surface of the semiconductor substrate.
12. 12. A semiconductor structure, comprising: a drift region of a first conductivity type on an upper surface of a semiconductor substrate of the first conductivity type, the drift region and the semiconductor substrate comprising polysilicon carbide; A JFET region of the first conductivity type disposed over the drift region, the JFET region including a vertical portion and a horizontal portion; A pair of channel regions disposed along the vertical and horizontal portions of the JFET region; a pair of source regions adjacent to the JFET region, each source region being bordered by a respective channel region and a first doped semiconductor region, and A schottky electrode adjacent to the first doped semiconductor region, wherein an oxide layer electrically isolates the schottky electrode from the first doped semiconductor region, wherein the oxide layer covers vertically opposite sidewalls of the schottky electrode, and a gap at a bottom portion of the oxide layer allows the schottky electrode to contact a second doped semiconductor region within the drift region.
13. 13. The semiconductor structure of claim 12, wherein the schottky electrode adjacent to the first doped semiconductor region comprises: A polysilicon carbide layer substantially fills the trench in the drift region.
14. 14. The semiconductor structure of claim 13, wherein the schottky electrode in contact with the second doped semiconductor region provides a schottky barrier rectifier integrated within the semiconductor structure.
15. 15. The semiconductor structure of claim 12 wherein the schottky electrode and the pair of source regions are electrically connected to a source terminal.
16. 16. The semiconductor structure of claim 12, further comprising: and a drain terminal disposed on a bottom surface of the semiconductor substrate.
17. 17. A semiconductor structure, comprising: a drift region of a first conductivity type on an upper surface of a semiconductor substrate of the first conductivity type, the drift region and the semiconductor substrate comprising polysilicon carbide; a trench extending into the drift region; a polysilicon layer disposed within the trench; an oxide layer disposed on opposite vertical sidewalls of the polysilicon layer and between an upper portion of the polysilicon layer and a lower portion of the polysilicon layer, a bottom portion of the oxide layer including a gap, and A second doped semiconductor region within the drift region, wherein the gap on the bottom portion of the oxide layer allows the lower portion of the polysilicon layer to contact the doped semiconductor region.
18. 18. The semiconductor structure of claim 17, wherein the upper portion of the polysilicon layer comprises a gate electrode and the lower portion of the polysilicon layer comprises a schottky electrode, wherein the oxide layer electrically isolates the gate electrode from the schottky electrode.
19. 19. The semiconductor structure of claim 18, wherein the schottky electrode in contact with the doped semiconductor region provides a schottky barrier rectifier integrated within the semiconductor structure.
20. 20. The semiconductor structure of claim 17, further comprising: a first doped semiconductor region between a pair of channel regions and over a base region disposed over the JFET region, wherein the trench is adjacent to at least one of the pair of channel regions; A pair of source regions disposed over respective ones of the pair of channel regions; A source terminal disposed over the pair of source regions, and And a drain terminal disposed on a bottom surface of the semiconductor substrate.

Description

Silicon carbide MOSFET with integrated polysilicon silicon carbide heterojunction diode Technical Field The present invention relates generally to the field of semiconductor devices, and more particularly to silicon carbide metal oxide semiconductor field effect transistors. Background Despite having similar design elements, silicon carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have higher blocking voltages and higher thermal conductivities than silicon (Si) MOSFETs. SiC MOSFETs are used in medium and high voltage power systems because they can achieve higher switching frequencies and higher efficiencies while reducing system size and redundancy requirements. Disclosure of Invention According to embodiments of the present disclosure, a semiconductor structure may include a semiconductor substrate of a first conductivity type. The semiconductor substrate may have an upper surface and a bottom surface. The semiconductor substrate may be formed of polycrystalline silicon carbide. The semiconductor structure may further include a drift region of the first conductivity type on an upper surface of the semiconductor substrate. The semiconductor structure may further include a first region of the upper surface of the semiconductor substrate, the first region including a formation region of the transistor. The semiconductor structure may further include a second region of the upper surface of the semiconductor substrate adjacent to the first region and including a formation region of the schottky barrier diode. According to another embodiment of the present disclosure, a semiconductor structure may include a drift region of a first conductivity type located on an upper surface of a semiconductor substrate of the first conductivity type. The drift region and the semiconductor substrate may comprise polysilicon carbide. The semiconductor structure may further include a JFET region of the first conductivity type disposed over the drift region. The JFET region may include a vertical portion and a horizontal portion. The semiconductor structure may further include a pair of channel regions disposed along the vertical and horizontal portions of the JFET region. The semiconductor structure may further include a pair of source regions adjacent to the JFET region. Each source region may be adjoined by a respective channel region and a first doped semiconductor region. The semiconductor structure may further include a schottky electrode adjacent the first doped semiconductor region, wherein an oxide layer electrically isolates the schottky electrode from the first doped semiconductor region, wherein the oxide layer covers vertically opposite sidewalls of the schottky electrode, and a gap at a bottom portion of the oxide layer allows the schottky electrode to contact a second doped semiconductor region located within the drift region. According to another embodiment of the present disclosure, a semiconductor structure may include a drift region of a first conductivity type located on an upper surface of a semiconductor substrate of the first conductivity type. The drift region and the semiconductor substrate may comprise polysilicon carbide. The semiconductor structure may further include a trench extending into the drift region and a polysilicon layer disposed within the trench. The semiconductor structure may further include an oxide layer disposed on opposite vertical sidewalls of the polysilicon layer and between an upper portion of the polysilicon layer and a lower portion of the polysilicon layer. The bottom portion of the oxide layer may include a gap. The semiconductor structure may further include a doped semiconductor region within the drift region. The gap on the bottom portion of the oxide layer may allow a lower portion of the polysilicon layer to contact the doped semiconductor region. Drawings The following detailed description is given by way of example only, and is not intended to limit the invention thereto, and will be better understood in conjunction with the accompanying drawings in which: Fig. 1 is a cross-sectional view of a semiconductor structure at an intermediate step during a semiconductor fabrication process in accordance with an embodiment of the present disclosure; fig. 2 is a cross-sectional view of a semiconductor structure after forming an oxide layer within a trench in accordance with an embodiment of the present disclosure; fig. 3 is a cross-sectional view of a semiconductor structure after forming a nitride layer over an oxide layer in accordance with an embodiment of the present disclosure; fig. 4 is a cross-sectional view of a semiconductor structure after formation of a photoresist layer in accordance with an embodiment of the present disclosure; Fig. 5 is a cross-sectional view of a semiconductor structure after patterning a photoresist layer and etching a nitride layer in accordance with an embodiment of the present disclosure; fig. 6 is a cross-sectional v