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CN-122002882-A - Transistor device and manufacturing method thereof

CN122002882ACN 122002882 ACN122002882 ACN 122002882ACN-122002882-A

Abstract

The present disclosure provides a transistor device and a method of fabricating the same. The transistor device comprises a channel layer, a barrier layer, a grid electrode, a first electrode, a second electrode, a first connecting block, a second connecting block and a dielectric layer, wherein the barrier layer is laminated on the channel layer, the dielectric layer is laminated on the barrier layer, the grid electrode is positioned on the dielectric layer, the contact surface of the channel layer and the barrier layer is provided with two-dimensional electron gas, the two-dimensional electron gas comprises an active area and a resistance area which are mutually separated, the resistance area is of an annular structure surrounding the active area and is provided with an opening, the first electrode and the second electrode penetrate through the dielectric layer and the barrier layer to be in contact with the active area, the first connecting block and the second connecting block penetrate through the dielectric layer and the barrier layer to be in contact with two sides of the opening of the resistance area, and the first connecting block and the grid electrode are electrically connected.

Inventors

  • ZHANG ZHONGYU
  • WANG JIANGBO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251219

Claims (10)

  1. 1. The transistor device is characterized by comprising a channel layer (101), a barrier layer (102), a grid electrode (103), a first electrode (104), a second electrode (105), a first connecting block (106), a second connecting block (107) and a dielectric layer (108); The barrier layer (102) is laminated on the channel layer (101), the dielectric layer (108) is laminated on the barrier layer (102), and the grid electrode (103) is positioned on the dielectric layer (108); the contact surface of the channel layer (101) and the barrier layer (102) is provided with a two-dimensional electron gas, the two-dimensional electron gas comprises an active region (201) and a resistance region (202) which are mutually spaced, the resistance region (202) is of a ring-shaped structure surrounding the active region (201), and the resistance region (202) is provided with an opening; The first electrode (104) and the second electrode (105) penetrate through the dielectric layer (108) and the barrier layer (102) to be in contact with the active region (201), the first connection block (106) and the second connection block (107) penetrate through the dielectric layer (108) and the barrier layer (102) to be in contact with two sides of an opening of the resistor region (202), and the first connection block (106) is electrically connected with the grid electrode (103).
  2. 2. The transistor device according to claim 1, wherein the active region (201) is rectangular, circular or elliptical and the resistive region (202) is annular in shape formed by a straight line, an arc line or a wavy line.
  3. 3. The transistor device according to claim 1, wherein the resistive region (202) has a circular width of 1-10 μm, and the circular perimeter of the resistive region (202) is positively correlated with a target resistance value.
  4. 4. The transistor device according to claim 1, wherein the minimum distance between the resistive region (202) and the active region (201) is 100 nm-100 μm.
  5. 5. A transistor device according to claim 1, characterized in that the resistive region (202) is provided with two connection portions (2020) at the openings, the two connection portions (2020) being in ohmic contact with the first connection block (106) and the second connection block (107), respectively.
  6. 6. The transistor device according to any of claims 1 to 5, further comprising a first passivation layer (109), a gate pad (110), a resistive pad (111), a first pad (112) and a second pad (113); The first passivation layer (109) covers the dielectric layer (108), the first electrode (104), the second electrode (105), the first connection block (106) and the second connection block (107); The gate pad (110) is in contact with the first connection block (106) through the first passivation layer (109), the resistor pad (111) is in contact with the second connection block (107) through the first passivation layer (109), the first pad (112) is electrically connected with the first electrode (104), and the second pad (113) is electrically connected with the second electrode (105).
  7. 7. A method of fabricating a transistor device, the method comprising: manufacturing a gate dielectric layer on an epitaxial layer, wherein the epitaxial layer comprises a channel layer and a barrier layer, and the contact surface of the channel layer and the barrier layer is provided with two-dimensional electron gas; Performing ion implantation on the gate dielectric layer and the epitaxial layer to enable the two-dimensional electron gas to form an active region and a resistance region which are mutually spaced, wherein the resistance region is of an annular structure surrounding the active region, and the resistance region is provided with an opening; The method comprises the steps of manufacturing a grid electrode, a first electrode, a second electrode, a first connecting block and a second connecting block, wherein the grid electrode is located on the dielectric layer, the first electrode and the second electrode penetrate through the dielectric layer and the barrier layer to be in contact with the active region, the first connecting block and the second connecting block penetrate through the dielectric layer and the barrier layer to be in contact with two sides of an opening of the resistance region, and the first connecting block is electrically connected with the grid electrode.
  8. 8. The method of claim 7, wherein ion implanting the gate dielectric layer and the epitaxial layer comprises: depositing a second passivation layer on the gate dielectric layer; Patterning the second passivation layer to cover the positions corresponding to the active region and the resistor region; And under the shielding of the second passivation layer, carrying out ion implantation on the gate dielectric layer and the epitaxial layer, and removing the two-dimensional electron gas in the ion implantation area.
  9. 9. The method of claim 8, wherein ion implanting the gate dielectric layer and the epitaxial layer comprises: And carrying out N ion implantation on the gate dielectric layer and the epitaxial layer, wherein the implantation times are 1-5 times, the implantation energy is 10-300 Kev, and the implantation dosage is 1E 17-1E 20cm -2 .
  10. 10. The method according to any one of claims 7 to 9, further comprising: manufacturing a first passivation layer, wherein the first passivation layer covers the dielectric layer, the first electrode, the second electrode, the first connecting block and the second connecting block; the manufacturing method comprises the steps of manufacturing a grid electrode bonding pad, a resistor bonding pad, a first bonding pad and a second bonding pad, wherein the grid electrode bonding pad passes through the first passivation layer to be in contact with the first connecting block, the resistor bonding pad passes through the first passivation layer to be in contact with the second connecting block, the first bonding pad is electrically connected with the first electrode, and the second bonding pad is electrically connected with the second electrode.

Description

Transistor device and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor technologies, and in particular, to a transistor device and a method for manufacturing the same. Background In the field of electronic circuit design, transistors such as high electron mobility transistors (High Electron Mobility Transistor, HEMT) are often used in combination with resistors, i.e., the transistors and resistors are connected together by packaging for integration. However, the integration method not only has complex manufacturing procedures, but also causes large area occupied by the transistor plus resistor, which is unfavorable for the integration level of the circuit. Disclosure of Invention The embodiment of the disclosure provides a transistor device and a manufacturing method thereof, which can reduce the procedures of collocating and using transistors and resistors and improve the integration level. The technical scheme is as follows: In one aspect, a transistor device is provided that includes a channel layer, a barrier layer, a gate electrode, a first electrode, a second electrode, a first connection block, a second connection block, a dielectric layer; The barrier layer is laminated on the channel layer, the dielectric layer is laminated on the barrier layer, and the grid electrode is positioned on the dielectric layer; The contact surface of the channel layer and the barrier layer is provided with a two-dimensional electron gas, the two-dimensional electron gas comprises an active area and a resistance area which are mutually spaced, the resistance area is of an annular structure surrounding the active area, and the resistance area is provided with an opening; The first electrode and the second electrode pass through the dielectric layer and the barrier layer to be in contact with the active region, the first connecting block and the second connecting block pass through the dielectric layer and the barrier layer to be in contact with two sides of the opening of the resistance region, and the first connecting block is electrically connected with the grid electrode. Optionally, the active area is rectangular, circular or elliptical, and the resistive area is annular formed by straight lines, arcs or wavy lines. Optionally, the annular width of the resistance region is 1-10 μm, and the annular perimeter of the resistance region is positively correlated with the target resistance value. Optionally, the minimum distance between the resistance region and the active region is 100 nm-100 μm. Optionally, the resistor area is provided with two connection parts at the opening, and the two connection parts are respectively in ohmic contact with the first connection block and the second connection block. Optionally, the transistor device further comprises a first passivation layer, a gate pad, a resistor pad, a first pad and a second pad; the first passivation layer covers the dielectric layer, the first electrode, the second electrode, the first connection block and the second connection block; the grid electrode bonding pad penetrates through the first passivation layer to be in contact with the first connecting block, the resistor bonding pad penetrates through the first passivation layer to be in contact with the second connecting block, the first bonding pad is electrically connected with the first electrode, and the second bonding pad is electrically connected with the second electrode. In another aspect, a method for fabricating a transistor device is provided, the method comprising: manufacturing a gate dielectric layer on an epitaxial layer, wherein the epitaxial layer comprises a channel layer and a barrier layer, and the contact surface of the channel layer and the barrier layer is provided with two-dimensional electron gas; Performing ion implantation on the gate dielectric layer and the epitaxial layer to enable the two-dimensional electron gas to form an active region and a resistance region which are mutually spaced, wherein the resistance region is of an annular structure surrounding the active region, and the resistance region is provided with an opening; The method comprises the steps of manufacturing a grid electrode, a first electrode, a second electrode, a first connecting block and a second connecting block, wherein the grid electrode is located on the dielectric layer, the first electrode and the second electrode penetrate through the dielectric layer and the barrier layer to be in contact with the active region, the first connecting block and the second connecting block penetrate through the dielectric layer and the barrier layer to be in contact with two sides of an opening of the resistance region, and the first connecting block is electrically connected with the grid electrode. Optionally, performing ion implantation on the gate dielectric layer and the epitaxial layer, including: depositing a second passivation layer on the gate dielectric