CN-122002883-A - Monolithic integrated structure of transverse and longitudinal devices, manufacturing method and equivalent circuit

CN122002883ACN 122002883 ACN122002883 ACN 122002883ACN-122002883-A

Abstract

The invention discloses a monolithic integrated structure of a transverse and longitudinal device, a manufacturing method and an equivalent circuit, wherein the manufacturing method is a monolithic integrated process compatible with the process, avoids complex processes such as secondary epitaxy and the like in the existing monolithic integrated process, minimizes process conflict of manufacturing steps of a transverse GaN low-voltage transistor and a vertical GaN high-voltage transistor, realizes a high-performance driving circuit formed by the transverse GaN low-voltage transistor and a high-efficiency power switch of the vertical GaN high-voltage transistor on a single chip, fully exerts the performance potential of GaN through monolithic integration of the transverse and longitudinal device, fundamentally eliminates parasitic parameters of traditional packaging, realizes power conversion of ultrahigh frequency, extremely small volume and extremely high efficiency, and can be better applied to the scenes such as DC-DC converters, main driving inverters, photovoltaic inverters, ultrahigh-speed chargers and 5G base station power amplifier power supplies of new energy automobiles.

Inventors

YOU SHUZHEN
ZHANG JINCHENG
HAO YUE
Yun Keqi
ZHOU TING
LEI YILONG
Jia Weixuan
LIU MING
GAO WENXIANG
CUI YANBIN
YU JIAYAO

Assignees

西安电子科技大学
西安电子科技大学广州研究院

Dates

Publication Date: 20260508
Application Date: 20251226

Claims (10)

1. A method for monolithically integrating a lateral device, the method comprising: Acquiring a substrate, and sequentially growing an n-GaN drift layer, a p-GaN current blocking layer, an n+ GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer and a pGaN cap layer on the substrate; etching pGaN cap layers at two ends of the device until reaching the upper surface of the n+ GaN heavily doped layer to form a mesa isolation region at one side of the device and a vertical device manufacturing region at the other side, wherein a transverse device manufacturing region and an equivalent resistance manufacturing region are formed between the mesa isolation region and the vertical device manufacturing region; continuing to etch the n+ GaN heavily doped layers at the two ends of the device until the n-GaN drift layer is formed, so that mesa isolation regions are finally formed at the two sides of the device; etching the n+ GaN heavily doped layer in the vertical device manufacturing area until the n-GaN drift layer is formed, so as to form a grid groove of the vertical device; Etching part of pGaN cap layers at intervals in a transverse device manufacturing area until reaching the upper surface of the AlGaN barrier layer, wherein a plurality of reserved pGaN cap layers are used for manufacturing a transverse GaN low-voltage transistor, and etching all pGaN cap layers in an equivalent resistance manufacturing area until reaching the upper surface of the AlGaN barrier layer; respectively performing ion implantation between adjacent pGaN cap layers in the transverse device manufacturing area, between the transverse device manufacturing area and the equivalent resistance manufacturing area, and between the equivalent resistance manufacturing area and the vertical device manufacturing area to form N implantation areas; depositing a passivation layer on the surface of the whole device; etching the passivation layer of the grid electrode area at the transverse device manufacturing area to expose the pGaN cap layers, forming a grid electrode on each exposed pGaN cap layer, and forming a grid electrode in the grid electrode groove of the vertical device manufacturing area; Etching passivation layers of source and drain regions at the equivalent resistance manufacturing region and the transverse device manufacturing region until reaching the upper surface of the AlGaN barrier layer, forming a source electrode and a drain electrode on the exposed AlGaN barrier layer to form an equivalent resistance device and a plurality of transverse GaN low-voltage transistors, etching the passivation layer of the source electrode region at the vertical device manufacturing region until reaching the upper surface of the n+ GaN heavily doped layer, forming two source electrodes on the exposed n+ GaN heavily doped layer, and forming a drain electrode on the lower surface of the substrate to form a vertical GaN high-voltage transistor; and leading out electrodes above the source electrode, the drain electrode and the grid electrode to form a monolithic integrated structure of the vertical GaN high-voltage transistor and the lateral GaN low-voltage transistor.
2. The method of fabricating a lateral and longitudinal device of claim 1, wherein the N implant region has an ion implant depth up to within the n+ GaN heavily doped layer.
3. The method for fabricating a lateral/longitudinal device according to claim 1, wherein in the lateral device fabrication region, a plurality of lateral GaN low-voltage transistors are formed by sequentially stacking a substrate, an n-GaN drift layer, a p-GaN layer current blocking layer, an n+ GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, a plurality of pGaN cap layers, and a gate electrode, a source electrode, and a drain electrode corresponding to the lateral device fabrication region from bottom to top.
4. The method for fabricating a lateral/longitudinal device according to claim 1, wherein in the equivalent resistance fabrication region, the equivalent resistance device is formed by sequentially stacking a substrate, an n-GaN drift layer, a p-GaN layer current blocking layer, an n+ GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer, and a source and a drain corresponding to the equivalent resistance fabrication region from bottom to top.
5. The method for fabricating a vertical/horizontal device according to claim 1, wherein the vertical GaN high-voltage transistor is formed by sequentially stacking, from bottom to top, a drain electrode, a substrate, an n-GaN drift layer, a p-GaN layer current blocking layer, an n+ GaN heavily doped layer, a GaN channel layer, and a gate electrode and two source electrodes corresponding to the vertical device fabrication region.
6. The method for manufacturing the single-chip integration of the lateral and longitudinal devices according to claim 1, wherein after the pGaN cap layers are etched at intervals in the lateral device manufacturing area, three pGaN cap layers are reserved for manufacturing the lateral GaN low-voltage transistors, so that the N injection area divides the lateral device manufacturing area into a first lateral device sub-area, a second lateral device sub-area and a third lateral device sub-area, and each of the first lateral device sub-area, the second lateral device sub-area and the third lateral device sub-area respectively comprises a corresponding gate electrode, a source electrode and a drain electrode, so that the first lateral GaN low-voltage transistor, the second lateral GaN low-voltage transistor and the third lateral GaN low-voltage transistor are formed.
7. The method for monolithically integrated fabrication of a lateral and longitudinal device according to claim 6, wherein extracting electrodes above the source electrode, the drain electrode, and the gate electrode comprises: The grid electrode of the first transverse GaN low-voltage transistor and the grid electrode of the second transverse GaN low-voltage transistor are connected and serve as input ends, the source electrode of the first transverse GaN low-voltage transistor, the source electrode of the second transverse GaN low-voltage transistor and the two source electrodes of the vertical GaN high-voltage transistor are grounded, the drain electrode of the second transverse GaN low-voltage transistor, the source electrode of the third transverse GaN low-voltage transistor and the grid electrode of the vertical GaN high-voltage transistor are connected and serve as output ends, the drain electrode of the third transverse GaN low-voltage transistor and the drain electrode of the equivalent resistance device are connected with a power supply VDD, the drain electrode of the vertical GaN high-voltage transistor is connected with an external circuit, and the drain electrode of the first transverse GaN low-voltage transistor is connected with the grid electrode of the third transverse GaN low-voltage transistor and the source electrode of the equivalent resistance device.
8. The monolithic integrated structure of the transverse and longitudinal devices is characterized in that the monolithic integrated structure is manufactured according to the monolithic integrated manufacturing method of the transverse and longitudinal devices according to any one of claims 1-7.
9. A monolithically integrated equivalent circuit of a lateral device, wherein the equivalent circuit is equivalent to the monolithically integrated structure of a lateral device according to claim 8.
10. The monolithically integrated equivalent circuit of a lateral and longitudinal device according to claim 9, wherein the equivalent circuit comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, and a resistor R1, wherein the transistor M1, the transistor M2, and the transistor M3 are respectively lateral GaN low voltage transistors, the transistor M4 is a vertical GaN high voltage transistor, and the resistor R1 is an equivalent resistor device.

Description

Monolithic integrated structure of transverse and longitudinal devices, manufacturing method and equivalent circuit Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to a monolithic integrated structure of a transverse and longitudinal device, a manufacturing method and an equivalent circuit. Background Gallium nitride as a third generation semiconductor has shown great potential in the field of power electronics. The transverse GaN HEMT (High Electron Mobility Transistor ) uses two-dimensional electron gas generated by AlGaN/GaN heterojunction as a conducting channel, and has the advantages of high electron mobility, high switching speed and relatively mature manufacturing process, is very suitable for manufacturing logic and control circuits with low voltage and high frequency, but the voltage resistance is generally dependent on the increase of the gate-drain spacing, so that the chip area utilization rate is low in high voltage application. The vertical GaN device has the advantages that the current flows vertically in the chip, the high breakdown voltage and the high current density are easy to realize, the chip area utilization rate is high, and the vertical GaN device is an ideal high-voltage power tube. In the existing monolithic integration scheme of the lateral and longitudinal devices, complex processes such as secondary epitaxy and the like are generally performed on a pre-patterned substrate so as to form lateral transistors and vertical transistors respectively. The vertical transistor is used as a power switch, has excellent area efficiency and high voltage performance, but only has a discrete vertical device scheme at present, and a single-chip integration scheme for directly and efficiently controlling the vertical power transistor by the transverse HEMT driving circuit is not seen. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a monolithic integrated structure of a transverse and longitudinal device, a manufacturing method and an equivalent circuit. The technical problems to be solved by the invention are realized by the following technical scheme: in a first aspect, an embodiment of the present invention provides a method for monolithically integrating a lateral device, where the method includes: Acquiring a substrate, and sequentially growing an n-GaN drift layer, a p-GaN current blocking layer, an n+ GaN heavily doped layer, a GaN channel layer, an AlGaN barrier layer and a pGaN cap layer on the substrate; etching pGaN cap layers at two ends of the device until reaching the upper surface of the n+ GaN heavily doped layer to form a mesa isolation region at one side of the device and a vertical device manufacturing region at the other side, wherein a transverse device manufacturing region and an equivalent resistance manufacturing region are formed between the mesa isolation region and the vertical device manufacturing region; continuing to etch the n+ GaN heavily doped layers at the two ends of the device until the n-GaN drift layer is formed, so that mesa isolation regions are finally formed at the two sides of the device; etching the n+ GaN heavily doped layer in the vertical device manufacturing area until the n-GaN drift layer is formed, so as to form a grid groove of the vertical device; Etching part of pGaN cap layers at intervals in a transverse device manufacturing area until reaching the upper surface of the AlGaN barrier layer, wherein a plurality of reserved pGaN cap layers are used for manufacturing a transverse GaN low-voltage transistor, and etching all pGaN cap layers in an equivalent resistance manufacturing area until reaching the upper surface of the AlGaN barrier layer; respectively performing ion implantation between adjacent pGaN cap layers in the transverse device manufacturing area, between the transverse device manufacturing area and the equivalent resistance manufacturing area, and between the equivalent resistance manufacturing area and the vertical device manufacturing area to form N implantation areas; depositing a passivation layer on the surface of the whole device; etching the passivation layer of the grid electrode area at the transverse device manufacturing area to expose the pGaN cap layers, forming a grid electrode on each exposed pGaN cap layer, and forming a grid electrode in the grid electrode groove of the vertical device manufacturing area; Etching passivation layers of source and drain regions at the equivalent resistance manufacturing region and the transverse device manufacturing region until reaching the upper surface of the AlGaN barrier layer, forming a source electrode and a drain electrode on the exposed AlGaN barrier layer to form an equivalent resistance device and a plurality of transverse GaN low-voltage transistors, etching the passivation layer of the source electrode region at the vertical device manufacturing region until reachin