CN-122002884-A - Semiconductor device and method for manufacturing the same

CN122002884ACN 122002884 ACN122002884 ACN 122002884ACN-122002884-A

Abstract

A method of fabricating a semiconductor device includes alternately depositing a sacrificial layer and a channel layer over a substrate such that a second channel layer underlying a first channel layer is thinner than the first channel layer, patterning a semiconductor stack to form a fin, recessing the fin to form source/drain openings, and epitaxially depositing a semiconductor material in the source/drain openings to form a source/drain structure. The method further includes removing the sacrificial layer such that a surface of the channel layer is exposed, depositing a gate dielectric over the surface of the channel layer and a conductive material over the gate dielectric to form a gate electrode around the channel layer, and depositing a conductive material over the source/drain structure in the source/drain opening to form a source/drain contact having a bottom surface below a bottom surface of the first channel layer. The embodiment of the application also relates to a semiconductor device.

Inventors

LIN DAJUN
SHEN PINJUN
ZHANG ZHIHAO
LIAO ZHONGZHI

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260508
Application Date: 20251229
Priority Date: 20250414

Claims (10)

1. A method of manufacturing a semiconductor device, comprising: Alternately depositing a sacrificial layer and a channel layer to form a semiconductor stack over a substrate, wherein the channel layer includes a first channel layer and a second channel layer located below the first channel layer Bao Yu the first channel layer; Patterning the semiconductor stack to form a fin; Recessing the fin in the source/drain regions to form source/drain openings; epitaxially depositing a semiconductor material in the source/drain openings to form source/drain structures; removing the sacrificial layer in a channel region adjacent to the source/drain regions such that a surface of the channel layer is exposed; Depositing a gate dielectric over the surface of the channel layer and a conductive material over the gate dielectric to form a gate electrode surrounding the channel layer, and A conductive material is deposited in the source/drain openings over the source/drain structures to form source/drain contacts having a bottom surface below a bottom surface of the first channel layer.
2. The method of claim 1, further comprising: prior to epitaxially depositing the semiconductor material to form the source/drain structures: Epitaxially depositing an undoped semiconductor layer over the surface of the source/drain openings, and A first isolation dielectric layer is deposited over the undoped semiconductor layer.
3. The method according to claim 1, wherein: the first channel layer has a first thickness and the second channel layer has a second thickness; each of the first thickness and the second thickness is between 2nm and 10nm, and The difference between the first thickness and the second thickness is between 0.5nm and 5nm.
4. The method of claim 1, further comprising: depositing an interlayer dielectric layer over the source/drain structures; etching the interlayer dielectric layer to form a contact trench through the interlayer dielectric layer, thereby exposing the source/drain structure; etching the source/drain structure through the contact trench to form an extended contact trench; Performing an implantation operation to form doped regions in the source/drain structure through the extension contact trench, and The source/drain contacts are formed in the extended contact trenches over the source/drain structures.
5. The method of claim 4, further comprising: forming a liner on sidewalls of the contact trench prior to etching the source/drain structure; forming a silicide layer over the doped region, and The source/drain contacts are formed over the silicide layer.
6. The method of claim 5, wherein alternately depositing the sacrificial layer and the channel layer to form the semiconductor stack further comprises depositing at least three channel layers such that a third channel layer is formed below the second channel layer.
7. The method of claim 6, wherein the at least three channel layers comprise a thinnest channel layer closest to the doped region.
8. The method of claim 2, further comprising: Forming a second isolation dielectric layer between the substrate and the bottom surface of the gate electrode; Wherein the first and second isolation dielectric layers comprise one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, or a high-k dielectric comprising one or more of HfO 2 、ZrO 2 、Al 2 O 3 、Ti O 2 、La 2 O 3 、Y 2 O 3 、BaSrTi O 3 .
9. A method of manufacturing a semiconductor device, comprising: Forming a full-gate field effect transistor structure comprising a plurality of stacked channel layers and source/drain regions, wherein the plurality of stacked channel layers comprises a first channel layer and a second channel layer located below the first channel layer Bao Yu of the first channel layer; Depositing a first epitaxial semiconductor layer over a surface of the source/drain regions; depositing a dielectric layer over the first epitaxial semiconductor layer; depositing a second epitaxial semiconductor layer over the dielectric layer; etching the second epitaxial semiconductor layer to form an extended contact trench extending to a depth below a bottom surface of the first channel layer, and A conductive material is deposited in the extended contact trench over the second epitaxial semiconductor layer to form source/drain contacts having a bottom surface below the bottom surface of the first channel layer.
10. A semiconductor device, comprising: A plurality of spaced apart stacked channel layers and source/drain regions, wherein the plurality of stacked channel layers includes a first channel layer and a second channel layer located below the first channel layer Bao Yu the first channel layer; A source/drain structure including a first epitaxial semiconductor layer formed over the source/drain regions such that the source/drain structure is in contact with the plurality of stacked channel layers, and Source/drain contacts are formed over the source/drain structures such that a bottom surface of the source/drain contacts is lower than a bottom surface of the first channel layer.

Description

Semiconductor device and method for manufacturing the same Technical Field Embodiments relate to a semiconductor device and a method of manufacturing the same. Background As the semiconductor industry advances to nanoscale technology nodes, it faces significant manufacturing and design challenges via the push for higher device density, enhanced performance, and reduced cost. These challenges have led to the adoption of three-dimensional structures such as multiple gate Field Effect Transistors (FETs), including fin field effect transistors (F inFET), full-gate field effect transistors (GAA-FETs), fork-lift-transistors, and Complementary FETs (CFETs). For example, in F inFET, the gate electrode is bordered on three sides by a gate dielectric layer. This configuration effectively provides control of the current through the channels because the gate surrounds the surfaces of the three channels. However, the fourth side forming the bottom of the channel is still far from the gate electrode and thus suffers from poor gate control. In contrast, GAA-FETs feature a gate electrode around all sides of the channel region, enabling more complete depletion of the channel and reduced short channel effects by steeper subthreshold swings and lower drain-induced barrier reduction. With the ever shrinking transistor sizes, further improvements in GAA-FET technology are needed to meet the ever-increasing demands of modern semiconductor devices. Disclosure of Invention An aspect of the present application provides a method of fabricating a semiconductor device comprising alternately depositing a sacrificial layer and a channel layer to form a semiconductor stack over a substrate, wherein the channel layer comprises a first channel layer and a second channel layer located below the first channel layer Bao Yu, patterning the semiconductor stack to form a fin, recessing the fin in a source/drain region to form a source/drain opening, epitaxially depositing a semiconductor material in the source/drain opening to form a source/drain structure, removing the sacrificial layer in a channel region adjacent to the source/drain region such that a surface of the channel layer is exposed, depositing a gate dielectric over the surface of the channel layer and a conductive material over the gate dielectric to form a gate electrode around the channel layer, and depositing a conductive material over the source/drain structure in the source/drain opening to form a source/drain contact having a bottom surface below a bottom surface of the first channel layer. Another aspect of the embodiments provides a method of manufacturing a semiconductor device comprising forming a full-loop gate field effect transistor structure comprising a plurality of stacked channel layers and source/drain regions, wherein the plurality of stacked channel layers comprises a first channel layer and a second channel layer located below the first channel layer Bao Yu the first channel layer, depositing a first epitaxial semiconductor layer over a surface of the source/drain regions, depositing a dielectric layer over the first epitaxial semiconductor layer, depositing a second epitaxial semiconductor layer over the dielectric layer, etching the second epitaxial semiconductor layer to form an extended contact trench extending to a depth below a bottom surface of the first channel layer, and depositing a conductive material over the second epitaxial semiconductor layer in the extended contact trench to form a source/drain contact having a bottom surface below the bottom surface of the first channel layer. Yet another aspect of an embodiment of the present application provides a semiconductor device comprising a plurality of spaced apart stacked channel layers and source/drain regions, wherein the plurality of stacked channel layers comprises a first channel layer and a second channel layer located below the first channel layer Bao Yu the first channel layer, a source/drain structure comprising a first epitaxial semiconductor layer formed above the source/drain regions such that the source/drain structure is in contact with the plurality of stacked channel layers, and a source/drain contact formed above the source/drain structure such that a bottom surface of the source/drain contact is lower than a bottom surface of the first channel layer. Drawings The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. The dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Fig. 1A is a first vertical cross-sectional view of a semiconductor device configured as a full-gate field effect transistor (GAAFET) in accordance with various embodiments; Fig. 1B is a second vertical c