CN-122002885-A - Process method for integrating multiple application voltage MOSFET devices

CN122002885ACN 122002885 ACN122002885 ACN 122002885ACN-122002885-A

Abstract

The invention provides a process method for integrating multiple application voltage MOSFET devices. The method defines first, second and third voltage device regions on a semiconductor substrate. The first and second conductivity type devices in the third voltage device region borrow corresponding well regions of the first or second voltage devices, respectively, in forming the well regions required for the first and second voltage devices. And opening a third voltage device region by using the newly added third application voltage photoetching mask, and performing one-step threshold voltage adjustment ion implantation, and simultaneously adjusting the threshold voltages of the two conductive type devices. And then forming a third gate dielectric layer and a gate structure. The invention can integrate the high-performance medium-voltage device with low cost on the basis of the existing double-gate oxide process by only adding one photomask and skillfully borrowing the well region and performing single injection step.

Inventors

ZHANG YINTONG
XU ZHAOZHAO
LIU DONGHUA
GAO CHAO

Assignees

华虹半导体(无锡)有限公司
上海华虹宏力半导体制造有限公司

Dates

Publication Date: 20260508
Application Date: 20260107

Claims (14)

1. A process for integrating multiple application voltage MOSFET devices, comprising: Providing a semiconductor substrate (101), and defining a first voltage device region, a second voltage device region and a third voltage device region on the semiconductor substrate (101), wherein the first voltage device region is used for forming a device of a first application voltage, the second voltage device region is used for forming a device of a second application voltage, and the third voltage device region is used for forming a device of a third application voltage, and the first application voltage is higher than the third application voltage, and the third application voltage is higher than the second application voltage; Forming a plurality of well regions required by a first voltage device and a plurality of well regions required by a second voltage device in the semiconductor substrate (101), wherein a third voltage first conductive type device in the third voltage device region borrows the first conductive type well region of the first voltage device or the first conductive type well region of the second voltage device, and a third voltage second conductive type device in the third voltage device region borrows the second conductive type well region of the second voltage device or the second conductive type well region of the first voltage device; Forming a first gate dielectric layer (203) on the semiconductor substrate (101), forming a third application voltage photoetching mask pattern by utilizing a photoetching process, and opening the third voltage device region by utilizing the third application voltage photoetching mask pattern; Performing threshold voltage adjusting ion implantation on the third voltage device region by taking the third application voltage photoetching mask pattern as a barrier, wherein the threshold voltage adjusting ion implantation forms a threshold adjusting layer (105) and simultaneously adjusts threshold voltages of the third voltage first conductive type device and the third voltage second conductive type device; removing the first gate dielectric layer (203) of the third voltage device region, and forming a third gate dielectric layer (106); And step six, depositing a gate conductive material and etching to form a gate structure (107).
2. The method of claim 1, wherein in step one, an isolation structure (102) is formed on the semiconductor substrate (101) to isolate the first voltage device region, the second voltage device region, and the third voltage device region from one another.
3. The method of claim 2, wherein in step one, the step of forming the isolation structure (102) comprises growing a pre-oxide layer (201) and a silicon nitride layer (202) on the semiconductor substrate (101), forming the isolation structure (102) using a shallow trench isolation process, and removing the silicon nitride layer (202).
4. The method of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type, the first conductivity type device is N-type metal-oxide-semiconductor field effect transistor, and the first conductivity type well region is P-type well region (103).
5. The method of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type, the first conductivity type device is a P-type metal-oxide-semiconductor field effect transistor, and the first conductivity type well region is an N-type well region.
6. The method of claim 4, wherein in the second step, the first voltage device is a high voltage device, the second voltage device is a low voltage device, the third voltage device is a medium voltage device, the third voltage first conductivity type device borrows the first conductivity type well region (103) of the first voltage device, and the third voltage second conductivity type device borrows the second conductivity type well region (104) of the second voltage device.
7. The method of claim 6, wherein in step four, the threshold voltage adjusting ion implantation is performed with a P-type impurity, and wherein the threshold voltage of the third voltage first conductivity type device is increased while the threshold voltage of the third voltage second conductivity type device is decreased by the threshold voltage adjusting ion implantation.
8. The method of claim 4, wherein in the fourth step, the threshold voltage adjusting ion implanted impurity is an N-type impurity, wherein the third voltage first conductivity type device borrows the first conductivity type well region of the second voltage device, and the third voltage second conductivity type device borrows the second conductivity type well region of the first voltage device.
9. The method for integrating multiple application voltage MOSFET devices as recited in claim 7, wherein said P-type impurity is boron.
10. The method for integrating multiple application voltage MOSFET devices as set forth in claim 9, wherein the threshold voltage adjusting ion implantation process comprises an implantation energy of 5 KeV-50 KeV, an implantation dose of 5.0e11-1.0e13, and an implantation angle of 0-10 °.
11. The method of claim 1, wherein in step three, the first gate dielectric layer (203) is a silicon oxide layer.
12. The method of claim 1, wherein in step five, after removing the first gate dielectric layer (203) of the third voltage device region, removing the third application voltage photolithographic reticle pattern, and thereafter growing the third gate dielectric layer (106) by a thermal oxidation process, wherein the thickness of the third gate dielectric layer (106) of the third voltage device region is between the thickness of the gate dielectric layer of the first voltage device region and the thickness of the gate dielectric layer of the second voltage device region.
13. The method of claim 1, further comprising the step of lightly doping the third voltage first-conductivity-type device with a first-conductivity-type lightly doping drain, and lightly doping the third voltage second-conductivity-type device with a second-conductivity-type lightly doping drain, wherein the third voltage first-conductivity-type device is subjected to a first-conductivity-type lightly doping drain implantation (108) process by the first voltage first-conductivity-type device, and the third voltage second-conductivity-type device is subjected to a second-conductivity-type lightly doping drain implantation (109) process by the first voltage second-conductivity-type device.
14. The method for integrating multiple application voltage MOSFET devices according to claim 13, wherein the method further comprises the steps of forming side wall dielectric layers (110) on two sides of the gate structure (107), performing ion implantation by taking the gate structure (107) and the side wall dielectric layers (110) as masks, performing first-conductivity-type heavily-doped source-drain implantation on the third-voltage first-conductivity-type device to form a first-conductivity-type source drain region (111), and performing second-conductivity-type heavily-doped source-drain implantation on the third-voltage second-conductivity-type device to form a second-conductivity-type source drain region (112).

Description

Process method for integrating multiple application voltage MOSFET devices Technical Field The invention relates to the technical field of semiconductors, in particular to a process method for integrating multiple application voltage MOSFET devices. Background With the increasing complexity of integrated circuit chip functionality, chip design often requires integration of metal-oxide-semiconductor field effect transistor (MOSFET) devices of different applied voltages to meet the requirements of different circuit modules. Common process platforms include Dual Gate oxide (Dual Gate) processes, which typically integrate High Voltage (High Voltage) devices and Low Voltage (Low Voltage) devices on the same chip, or tri-Gate oxide (TRIPLE GATE) processes, for integrating devices of more various Voltage levels. In the existing semiconductor manufacturing process, each device with a specific application voltage generally needs a specific Well region (Well), a threshold voltage adjustment implant, a gate dielectric layer and a source drain light doped (LDD) structure to ensure its electrical performance. Therefore, in general, every time a voltage-applied device is integrated in a chip, 3 to 5 layers of masks (masks) are added, and corresponding photolithography, implantation, and etching steps are required. For example, to add a device with a medium applied voltage (e.g., a 3.3V device) based on the existing Dual Gate process including high voltage and low voltage devices, separate well implant masks, separate threshold adjustment masks, and dedicated LDD masks are required for the medium voltage NMOS and PMOS, respectively, according to the conventional method. Although the performance of the new device can be independently regulated and controlled, the number of photomasks is greatly increased, so that the process cost and the production period are obviously increased, and the market competitiveness of the product is not facilitated. Therefore, how to flexibly integrate MOSFET devices with various application voltages on the existing process platform without significantly increasing the number of masks and the process cost is a technical problem to be solved in the current semiconductor manufacturing field. Disclosure of Invention In order to solve the problems of significant increase in process cost and prolonged production period caused by the addition of multiple layers of photomasks (for example, 3-5 layers) for each device integrated with one application voltage in a chip in the conventional semiconductor manufacturing process, the invention provides a process method for integrating multiple application voltage MOSFET devices. The invention provides a process method for integrating multiple application voltage MOSFET devices, which comprises the following steps: providing a semiconductor substrate, and defining a first voltage device region, a second voltage device region and a third voltage device region on the semiconductor substrate, wherein the first voltage device region is used for forming a device with a first application voltage, the second voltage device region is used for forming a device with a second application voltage, and the third voltage device region is used for forming a device with a third application voltage, and the first application voltage is higher than the third application voltage, and the third application voltage is higher than the second application voltage; Forming a plurality of well regions required by a first voltage device and a plurality of well regions required by a second voltage device in the semiconductor substrate, wherein a third voltage first conductive type device in the third voltage device region borrows the first conductive type well region of the first voltage device or the first conductive type well region of the second voltage device, and a third voltage second conductive type device in the third voltage device region borrows the second conductive type well region of the second voltage device or the second conductive type well region of the first voltage device; Forming a first grid dielectric layer on the semiconductor substrate, forming a third application voltage photoetching mask pattern by utilizing a photoetching process, and opening the third voltage device region by utilizing the third application voltage photoetching mask pattern; Performing threshold voltage adjusting ion implantation on the third voltage device region by taking the third application voltage photoetching mask pattern as a barrier, wherein the threshold voltage adjusting ion implantation forms a threshold adjusting layer and simultaneously adjusts threshold voltages of the third voltage first conductive type device and the third voltage second conductive type device; removing the first gate dielectric layer of the third voltage device region, and forming a third gate dielectric layer; And step six, depositing a gate conductive material and etching to form a gate structure. Preferabl