CN-122002886-A - Method for manufacturing semiconductor device and semiconductor device

CN122002886ACN 122002886 ACN122002886 ACN 122002886ACN-122002886-A

Abstract

The application relates to a preparation method of a semiconductor device and the semiconductor device, which comprise the steps of providing a semiconductor material layer, forming a first mask layer, forming a first opening exposing a first region of the semiconductor material layer, at least shielding a second region of the semiconductor material layer, performing a first ion implantation process on the first region based on the first mask layer, forming a first drift region of a first conductivity type, forming a second mask layer, forming a second opening exposing the second region, at least shielding the first region, performing a second ion implantation process on the second region based on the second mask layer, forming a first well region of the first conductivity type, wherein the second implantation concentration of the second ion implantation process is larger than that of the first ion implantation process, forming a second drift region of the second conductivity type, and forming a first source region and a first drain region respectively in the first well region and the second drift region. Thereby, the effect on the threshold voltage is reduced while improving the hot carrier effect.

Inventors

ZHAO LIANGLIANG
LI YONG
SUN WEI
ZHANG YIFAN

Assignees

芯联先锋集成电路制造(绍兴)有限公司

Dates

Publication Date: 20260508
Application Date: 20260204

Claims (10)

1. A method of manufacturing a semiconductor device, the method comprising: Providing a semiconductor material layer; Forming a first mask layer on the semiconductor material layer, wherein the first mask layer is provided with a first opening exposing a first area of the semiconductor material layer, and the first mask layer at least shields a second area of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region having a first conductivity type; Forming a second mask layer on the semiconductor material layer, wherein a second opening exposing the second region is formed in the second mask layer, and the second mask layer at least shields the first region; Performing a second ion implantation process on the second region based on the second mask layer to form a first well region with a first conductivity type, wherein the second ion implantation process has a second implantation concentration of first conductivity type ions greater than the first ion implantation process so that the first well region has a doping concentration greater than that of the first drift region; Forming a second drift region having a second conductivity type within the semiconductor material layer, wherein the first conductivity type and the second conductivity type are different; and forming a first source region and a first drain region in the first well region and the second drift region, respectively, wherein the first drift region and the first well region are used for forming a channel between the first source region and the first drain region.
2. The method for manufacturing a semiconductor device according to claim 1, wherein, Along the thickness direction of the semiconductor material layer, the projection of the first opening and the projection of the second opening are spaced from each other.
3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The first drift region comprises a first region and a first lateral diffusion region positioned at the periphery of the first region; The first well region comprises a second region and a second lateral diffusion region positioned at the periphery of the second region; a diffusion overlapping region is formed by the overlapping part of the first lateral diffusion region and the second lateral diffusion region; Wherein the net doping concentration of the first conductivity type ions of the diffusion overlap region is less than or equal to the net doping concentration of the first conductivity type ions of the second region.
4. The method for manufacturing a semiconductor device according to claim 1, wherein, The line width of the first opening is larger than or equal to the line width of the second opening.
5. The method for manufacturing a semiconductor device according to claim 4, wherein, The ratio of the line width of the first opening to the line width of the second opening is 1:1-2:1.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that the method further comprises: forming a third drift region of the semiconductor material layer having the first conductivity type in a third region of the semiconductor material layer, forming a second drain region in the third drift region, The first mask layer is further formed with a third opening exposing the third region, and ions are simultaneously implanted in the first region and the third region when the first ion implantation process is performed.
7. A semiconductor device, comprising: a layer of semiconductor material; A first drift region and a first well region, which are positioned in the semiconductor material layer and are all provided with a first conductivity type, wherein the bottom of the first well region is only adjacent to a region of the semiconductor material layer which is not doped to form the first drift region, and the doping concentration of the first well region is larger than that of the first drift region; a second drift region within the semiconductor material layer having a second conductivity type different from the first conductivity type; The first source region and the first drain region are respectively positioned in the first well region and the second drift region, and the first drift region and the first well region are used for forming a channel between the first source region and the first drain region.
8. The semiconductor device according to claim 7, wherein, The first drift region comprises a first region and a first lateral diffusion region positioned at the periphery of the first region; The first well region comprises a second region and a second lateral diffusion region positioned at the periphery of the second region; a diffusion overlapping region is formed by the overlapping part of the first lateral diffusion region and the second lateral diffusion region; Wherein the net doping concentration of the first conductivity type ions of the diffusion overlap region is less than or equal to the net doping concentration of the first conductivity type ions of the second region.
9. The semiconductor device according to claim 7, wherein, The width of the first drift region is greater than or equal to the width of the first well region along a direction perpendicular to the thickness of the semiconductor material layer.
10. The semiconductor device according to claim 7, further comprising: A third drift region with a first conductivity type and located in the semiconductor material layer, wherein the third drift region and the first drift region are formed by implantation based on the same mask layer in the same ion implantation process; and the second drain electrode region is positioned in the third drift region.

Description

Method for manufacturing semiconductor device and semiconductor device Technical Field The present application relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device. Background The BCD (Bipolar-CMOS-DMOS) process is an advanced manufacturing process that integrates Bipolar, CMOS (Complementary Metal-Oxide-Semiconductor) and DMOS (Double-Diffused Metal-Oxide-Semiconductor) on the same chip. The technology obviously reduces the chip area, reduces the system power consumption, improves the energy efficiency and the reliability, and is widely applied to the fields of power management, automobile electronics, audio amplifiers and the like. In the manufacture of integrated circuit chips, the reliability of semiconductor devices (e.g., transistors) is one of the key criteria for determining whether the chip can be used properly. Among them, HCI (Hot Carrier Inject, hot carrier injection) effect is one of the core problems that restrict device reliability. When the drain electrode end of the device is increased in voltage, collision ionization occurs in the channel region of the device, hot carriers are generated, the larger the collision ionization concentration is, the more high-energy hot carriers are generated, and the high-energy hot carriers pass through the gate dielectric, so that the HCI effect is aggravated. The HCI effect of the device is usually improved by changing the material of the device, for example, adopting a High-K material (such as HfO 2) as a gate dielectric, realizing higher capacitance density, reducing working voltage, or improving carrier mobility by stretching or compressing lattice through a strained silicon technology, reducing High electric Field requirement, optimizing the structure of the device, for example, forming a gradient doped region at the drain end through LDD (Lightly Doped Drain ), dispersing electric Field peaks, or reinforcing the control force of the gate to the channel by adopting a Fin FET (Fin Field-Effect Transistor, fin Field effect transistor) and the like, reducing working voltage, designing a system-level protection, for example, designing a dynamic voltage frequency regulating system for reducing the voltage according to load in real time, or integrating an HCI life prediction model through EDA (Electronic Design Automation ) tools, and optimizing wiring in the design stage. In addition, a new method for improving the HCI effect of the device has been proposed in the field in recent years. The drift region with low doping concentration and the well region with high doping concentration form a source end doping region, PN junction formed between the source end doping region and a drain end doping region (drain end drift region) is a graded junction, so that collision ionization concentration in a channel can be effectively reduced, and HCI is improved. Under the superposition of the doping concentration of the source end drift region, the doping concentration of the source end well region formed by the method is increased, so that the doping concentration of a channel is increased, the threshold voltage of the device is increased accordingly, and the starting power consumption of the device is increased. Therefore, how to improve HCI and reduce the influence on the threshold voltage is an urgent problem in the art. Disclosure of Invention In view of the above, embodiments of the present application provide a method for manufacturing a semiconductor device and a semiconductor device for solving at least one of the problems in the background art. In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, where the method includes: Providing a semiconductor material layer; Forming a first mask layer on the semiconductor material layer, wherein the first mask layer is provided with a first opening exposing a first area of the semiconductor material layer, and the first mask layer at least shields a second area of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region having a first conductivity type; Forming a second mask layer on the semiconductor material layer, wherein a second opening exposing the second region is formed in the second mask layer, and the second mask layer at least shields the first region; Performing a second ion implantation process on the second region based on the second mask layer to form a first well region with a first conductivity type, wherein the second ion implantation process has a second implantation concentration of first conductivity type ions greater than the first ion implantation process so that the first well region has a doping concentration greater than that of the first drift region; Forming a second drift region having a second conductivity type within the semiconductor