CN-122002887-A - Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The application provides a semiconductor structure, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor structure comprises the steps of manufacturing a plurality of first isolation structures on a substrate, manufacturing a first signal wire located between any two adjacent first isolation structures, manufacturing a first insulating layer covering the first isolation structures and the first signal wire, manufacturing a plurality of second isolation structures on the first insulating layer, manufacturing a second signal wire located between any two adjacent second isolation structures, manufacturing a second insulating layer covering the second isolation structures and the second signal wire, forming a plurality of through holes penetrating through the second insulating layer, the second signal wire and the first insulating layer, exposing the first signal wire at the bottoms of the through holes, and sequentially manufacturing a semiconductor layer, a gate insulating layer and a conductive layer which cover and fill the plurality of through holes in a conformal mode to obtain a plurality of transistors. The application can avoid the problem of holes, improve the problem of difference of transistor channel lengths, and greatly improve the stability and reliability of the process.

Inventors

• WANG WEI
• JIA LIBIN
• ZENG MING

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260508

Application Date

20241105

Claims (10)

1. 1. A method of fabricating a semiconductor structure, comprising: the first isolation structures are distributed along a first direction and extend along a second direction respectively, and the first direction and the second direction intersect and are parallel to the substrate; manufacturing a first signal line between any two adjacent first isolation structures; Manufacturing a first insulating layer covering the first isolation structure and the first signal line; A plurality of second isolation structures are manufactured on the first insulating layer, distributed along the second direction and respectively extended along the first direction; manufacturing a second signal line between any two adjacent second isolation structures; manufacturing a second insulating layer covering the second isolation structure and the second signal line; forming a plurality of through holes penetrating through the second insulating layer, the second signal lines and the first insulating layer, wherein the bottoms of the through holes are exposed out of the first signal lines; And sequentially manufacturing a semiconductor layer, a gate insulating layer and a conductive layer which at least cover and fill the plurality of through holes along with the shape to obtain a plurality of transistors.
2. 2. The method of manufacturing a semiconductor structure of claim 1, further comprising, prior to fabricating the plurality of first isolation structures on the substrate: manufacturing an interlayer insulating layer on a substrate; And fabricating a plurality of first isolation structures on the substrate, comprising: manufacturing a first isolation layer on the interlayer insulating layer; And patterning to form a plurality of first grooves which are sequentially distributed at intervals in the first direction and extend along the second direction, wherein the first grooves divide the first isolation layer into a plurality of first isolation structures.
3. 3. The method of manufacturing a semiconductor structure according to claim 2, wherein fabricating a first signal line between any adjacent two of the first isolation structures comprises: depositing a conductive material to form a first conductive layer, wherein the first conductive layer fills the first groove and covers the first isolation structure; And flattening until the first isolation structure is exposed, wherein the first conductive layer in any first groove forms a first signal line, and the first signal line is flush with the surface of the first isolation structure.
4. 4. The method of manufacturing a semiconductor structure according to claim 1, wherein fabricating a first insulating layer covering the first isolation structure and the first signal line, comprises: Forming the first insulating layer by adopting an atomic layer deposition process; and fabricating a plurality of second isolation structures on the first insulating layer, including: forming a second isolation layer by adopting an atomic layer deposition process; and patterning to form a plurality of second grooves which are sequentially distributed at intervals in the second direction and extend along the first direction, wherein the second grooves divide the second isolation layer into a plurality of second isolation structures.
5. 5. The method of manufacturing a semiconductor structure according to claim 4, wherein fabricating a second signal line between any adjacent two of the second isolation structures comprises: depositing a conductive material to form a second conductive layer, wherein the second conductive layer fills the second groove and covers the second isolation structure; And flattening until the second isolation structure is exposed, wherein the second conductive layer in any second groove forms a second signal line, and the second signal line is flush with the surface of the second isolation structure.
6. 6. The method of manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein manufacturing a second insulating layer that covers the second isolation structure and the second signal line, comprises: Forming the second insulating layer by adopting an atomic layer deposition process; and forming a plurality of through holes penetrating the second insulating layer, the second signal line, and the first insulating layer, including: And etching the second insulating layer, the second signal line and the first insulating layer to expose the first signal line, and forming a plurality of through holes distributed in an array in the first direction and the second direction.
7. 7. A semiconductor structure, comprising: the first isolation structures and the first signal lines are arranged on the substrate, are sequentially and alternately distributed along the first direction and respectively extend along the second direction; A first insulating layer disposed on each of the first isolation structures and each of the first signal lines; the second isolation structures and the second signal lines are arranged on the first insulating layer, are sequentially and alternately distributed along the second direction and extend along the first direction respectively; a second insulating layer disposed on each of the second isolation structures and each of the second signal lines; And the transistors comprise conductive layers at least extending along the direction vertical to the substrate, and a grid insulating layer and a semiconductor layer which are sequentially wound around the periphery of the conductive layers, wherein the semiconductor layer is electrically connected with the first signal line and the second signal line.
8. 8. The semiconductor structure of claim 7, comprising at least one of: The semiconductor structure further comprises an interlayer insulating layer, wherein the interlayer insulating layer is arranged on the substrate and is positioned on one side, close to the substrate, of each first isolation structure and each first signal line; The first signal line and the first isolation structure are flush with the surface of one side far away from the substrate; The second signal line and the second isolation structure are flush with the surface of the side far away from the substrate.
9. 9. The semiconductor structure of claim 7, comprising at least one of: the transistors are distributed in an array in the first direction and the second direction, a plurality of transistors distributed in sequence along the first direction are electrically connected with a second signal line, and a plurality of transistors distributed in sequence along the second direction are electrically connected with a first signal line; A semiconductor layer located between the first signal line and the second signal line serves as a channel region of the transistor, and a conductive layer corresponding to the channel region serves as a gate of the transistor; The first signal line serves as one of a source and a drain, and the second signal line serves as the other of the source and the drain.
10. 10. An electronic device, comprising: a semiconductor structure manufactured by the method for manufacturing a semiconductor structure as claimed in any one of claims 1 to 6, or The semiconductor structure of any one of claims 7 to 9.

Description

Semiconductor structure, manufacturing method thereof and electronic equipment Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and electronic equipment. Background With the development and progress of semiconductor technology, semiconductor devices are continuously developed toward miniaturization, high memory density, high integration, and low power consumption, and are also faced with problems and challenges from the aspects of processes and the like. Disclosure of Invention The application provides a semiconductor structure, a manufacturing method thereof and electronic equipment, which are used for solving the problems that holes are easy to generate when oxide is deposited between metals with smaller sizes in the related technology, and the stability of the channel length is easy to be influenced by the difference of thickness. In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: The first isolation structures are distributed along a first direction, extend along a second direction respectively, intersect the first direction and are parallel to the substrate; Manufacturing a first signal line between any two adjacent first isolation structures; Manufacturing a first insulating layer covering the first isolation structure and the first signal line; the first insulating layer is provided with a plurality of first isolation structures, and the first isolation structures are distributed along a first direction; manufacturing second signal lines between any two adjacent second isolation structures; Manufacturing a second insulating layer covering the second isolation structure and the second signal line; forming a plurality of through holes penetrating the second insulating layer, the second signal lines and the first insulating layer, wherein the first signal lines are exposed at the bottoms of the through holes; and sequentially manufacturing a semiconductor layer, a gate insulating layer and a conductive layer which at least cover and fill the plurality of through holes along the shape to obtain a plurality of transistors. In some alternative embodiments of the present application, before fabricating the plurality of first isolation structures on the substrate, the method further comprises: manufacturing an interlayer insulating layer on a substrate; And fabricating a plurality of first isolation structures on the substrate, comprising: Manufacturing a first isolation layer on the interlayer insulating layer; And patterning to form a plurality of first grooves which are sequentially distributed at intervals in the first direction and extend along the second direction, wherein the first grooves divide the first isolation layer into a plurality of first isolation structures. In some alternative embodiments of the present application, fabricating a first signal line between any two adjacent first isolation structures includes: depositing a conductive material to form a first conductive layer, wherein the first conductive layer fills the first groove and covers the first isolation structure; and flattening until the first isolation structure is exposed, wherein the first conductive layer in any first groove forms a first signal line, and the first signal line is flush with the surface of the first isolation structure. In some alternative embodiments of the present application, fabricating a first insulating layer covering the first isolation structure and the first signal line, includes: Forming a first insulating layer by adopting an atomic layer deposition process; And fabricating a plurality of second isolation structures on the first insulating layer, including: forming a second isolation layer by adopting an atomic layer deposition process; And patterning to form a plurality of second grooves which are sequentially distributed at intervals in the second direction and extend along the first direction, wherein the second grooves divide the second isolation layer into a plurality of second isolation structures. In some alternative embodiments of the present application, fabricating a second signal line between any two adjacent second isolation structures includes: Depositing a conductive material to form a second conductive layer, wherein the second conductive layer fills the second trench and covers the second isolation structure; And flattening until the second isolation structure is exposed, wherein the second conductive layer in any second groove forms a second signal line, and the second signal line is flush with the surface of the second isolation structure. In some alternative embodiments of the present application, fabricating a second insulating layer covering the second isolation structure and the second signal line, includes: forming a second insulating layer by adopting an atomic layer deposition process; An