CN-122002889-A - Integrated circuit device

Abstract

An integrated circuit device includes a substrate and a Metal Oxide Semiconductor Capacitor (MOSCAP) on the substrate. The MOSCAP includes a lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions on a substrate, and an upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions on the lower semiconductor device. The lower gate structure is electrically connected to both of the pair of upper source/drain regions.

Inventors

• Xin Xiaozong
• Pu Fanjin
• Xin Zongmen
• Pu Yongguo
• Xu Kangyi

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20251104

Priority Date

20250613

Claims (20)

1. 1. An integrated circuit device, comprising: A substrate, and A metal oxide semiconductor capacitor, on a substrate, the metal oxide semiconductor capacitor comprising: A lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions on a substrate, and An upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions on the lower semiconductor device, Wherein the lower gate structure is electrically connected to both of the pair of upper source/drain regions.
2. 2. The integrated circuit device of claim 1, wherein an upper gate structure is electrically connected to both of the pair of lower source/drain regions.
3. 3. The integrated circuit device of claim 1, wherein the metal oxide semiconductor capacitor further comprises an isolation region between the lower gate structure and the upper gate structure, and Wherein the lower gate structure is electrically separated from the upper gate structure by an isolation region.
4. 4. The integrated circuit device of claim 1, wherein the lower gate structure is configured to receive a first voltage, and Wherein the upper gate structure is configured to receive a second voltage different from the first voltage.
5. 5. The integrated circuit device of claim 1, wherein the lower semiconductor device further comprises a plurality of lower channel layers between the pair of lower source/drain regions, the plurality of lower channel layers being spaced apart from one another in a direction perpendicular to the upper surface of the substrate, and Wherein the upper semiconductor device further includes a plurality of upper channel layers between the pair of upper source/drain regions, the plurality of upper channel layers being spaced apart from each other in the direction.
6. 6. The integrated circuit device of claim 1, wherein the pair of lower source/drain regions have a first conductivity type, and Wherein the pair of upper source/drain regions have a second conductivity type different from the first conductivity type.
7. 7. The integrated circuit device of any of claims 1-6, wherein the lower gate structure and the upper gate structure are configured to receive a first voltage and a second voltage, respectively, and Wherein the metal oxide semiconductor capacitor is configured to have a maximum capacitance value when the first voltage and the second voltage cause both the lower semiconductor device and the upper semiconductor device to operate in the inversion region.
8. 8. An integrated circuit device, comprising: A substrate; A front side metal oxide metal capacitor on the first surface of the substrate, and A backside metal oxide metal capacitor electrically connected to the front side metal oxide metal capacitor on a second surface of the substrate opposite the first surface.
9. 9. The integrated circuit device of claim 8, wherein the back side metal oxide metal capacitor comprises an upper back side metallization pattern comprising a plurality of staggered upper back side fingers, and Wherein the plurality of staggered upper backside fingers extend in a first direction parallel to the first surface of the substrate and are spaced apart from each other in a second direction intersecting the first direction.
10. 10. The integrated circuit device of claim 9, further comprising a semiconductor device comprising a pair of source/drain regions and a gate structure between the pair of source/drain regions on the first surface of the substrate, Wherein the gate structure extends in a second direction and overlaps at least one of the plurality of staggered upper backside fingers in a third direction perpendicular to the first surface of the substrate.
11. 11. The integrated circuit device of claim 9, wherein the upper backside metallization pattern comprises a first upper backside metallization layer comprising a first staggered upper backside finger of the plurality of staggered upper backside fingers and a second upper backside metallization layer comprising a second staggered upper backside finger of the plurality of staggered upper backside fingers, Wherein the first upper backside metallization layer is capacitively coupled to the second upper backside metallization layer, an Wherein the back side metal oxide metal capacitor further comprises an insulating layer between the first upper back side metallization layer and the second upper back side metallization layer.
12. 12. The integrated circuit device of claim 9, wherein the back side metal oxide metal capacitor further comprises a lower back side metallization pattern on a lower surface of the upper back side metallization pattern, the lower back side metallization pattern comprising a plurality of staggered lower back side fingers, and Wherein the plurality of staggered lower backside fingers extend in a second direction and are spaced apart from each other in the first direction.
13. 13. The integrated circuit device of claim 12, wherein the back side metal oxide metal capacitor further comprises a back side insulating layer between the lower back side metallization pattern and the upper back side metallization pattern in a third direction perpendicular to the first surface of the substrate, and Wherein at least one of the plurality of staggered upper backside fingers overlaps at least one of the plurality of staggered lower backside fingers in a third direction.
14. 14. The integrated circuit device according to any one of claims 8 to 13, further comprising a metal oxide semiconductor capacitor, between the front side metal oxide metal capacitor and the back side metal oxide metal capacitor, Wherein the metal oxide semiconductor capacitor comprises: A lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions on a substrate, and An upper semiconductor device, on the lower semiconductor device, the upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions.
15. 15. The integrated circuit device of claim 14, further comprising an upper source/drain contact structure extending between the front side metal oxide metal capacitor and the back side metal oxide metal capacitor, wherein a first upper source/drain region of the pair of upper source/drain regions is electrically connected to both the front side metal oxide metal capacitor and the back side metal oxide metal capacitor through the upper source/drain contact structure.
16. 16. The integrated circuit device of claim 14, further comprising a lower source/drain contact structure extending between the front side metal oxide metal capacitor and the back side metal oxide metal capacitor, wherein a first lower source/drain region of the pair of lower source/drain regions is electrically connected to both the front side metal oxide metal capacitor and the back side metal oxide metal capacitor through the lower source/drain contact structure.
17. 17. An integrated circuit device, comprising: A substrate; A metal oxide semiconductor capacitor on the first surface of the substrate, and A backside metal oxide metal capacitor electrically connected to the metal oxide semiconductor capacitor on a second surface of the substrate opposite the first surface.
18. 18. The integrated circuit device of claim 17, wherein the metal oxide semiconductor capacitor comprises: A lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions on a substrate, and An upper semiconductor device, on the lower semiconductor device, the upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions.
19. 19. The integrated circuit device of claim 18, further comprising a lower gate contact extending into the substrate, wherein the lower gate structure is electrically connected to the backside metal oxide metal capacitor through the lower gate contact.
20. 20. The integrated circuit device of claim 18, further comprising a lower source/drain contact structure extending into the substrate, wherein a first lower source/drain region of the pair of lower source/drain regions is electrically connected to the backside metal oxide metal capacitor through the lower source/drain contact structure.

Description

Integrated circuit device Technical Field The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices including high density capacitors. Background Transistors in Integrated Circuit (IC) devices have been continuously reduced in size to shrink logic elements. This has led to the development of fully surrounding Gate (GAA) structures such as multi-bridge channel FETs (field effect transistors) (MBCFET TM) and nanoflake FETs (NSFETs). Furthermore, as technologies for increasing transistor density have continued to develop, three-dimensional (3D) device structures (such as stacked transistors) are being considered. The stacked transistor (or "transistor stack") may include a first transistor and a second transistor. The first transistor may be a first type transistor (e.g., an n-type metal oxide semiconductor (NMOS) transistor) and the second transistor may be a second type transistor (e.g., a p-type metal oxide semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other and thus may be part of a Complementary Metal Oxide Semiconductor (CMOS) structure. The first transistor and the second transistor may be stacked in any order (e.g., first on top of the second, or second on top of the first), resulting in a stack comprising an upper transistor and a lower transistor. Disclosure of Invention An integrated circuit device according to some embodiments herein may include a substrate, and a Metal Oxide Semiconductor Capacitor (MOSCAP) on the substrate, the MOSCAP including a lower semiconductor device on the substrate, the lower semiconductor device including a pair of lower source/drain regions and a lower gate structure between the pair of lower source/drain regions, and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device including a pair of upper source/drain regions and an upper gate structure between the pair of upper source/drain regions. The lower gate structure is electrically connected to both of the pair of upper source/drain regions. An integrated circuit device according to some embodiments herein may include a substrate, a front side Metal Oxide Metal Capacitor (MOMCAP) on a first surface of the substrate, and a back side MOMCAP capacitor on a second surface of the substrate opposite the first surface, the back side MOMCAP being electrically connected to the front side MOMCAP. An integrated circuit device according to some embodiments herein may include a substrate, a Metal Oxide Semiconductor Capacitor (MOSCAP) on a first surface of the substrate, and a backside Metal Oxide Metal Capacitor (MOMCAP) on a second surface of the substrate opposite the first surface, the backside MOMCAP electrically connected to the MOSCAP. Example embodiments of the present application stem in part from the recognition that by modifying existing architectures for forming three-dimensional (3D) stacked transistors, such as 3D stacked field effect transistors (3 DSFET), in integrated circuit devices, it may be advantageous to provide one or more high-density capacitors in an integrated circuit device, thereby simplifying the manufacturing process for and reducing the manufacturing costs associated with the high-density capacitors. For example, high density capacitors may be used as decoupling capacitors that help provide a stable voltage supply and/or filter noise within an integrated circuit device. Drawings Fig. 1 is a schematic cross-sectional view of a conventional integrated circuit device. Fig. 2A is a schematic block diagram of a transistor stack of an integrated circuit device, according to some embodiments. Fig. 2B is a schematic plan view of an integrated circuit device according to some embodiments. Fig. 2C is a schematic cross-sectional view taken along line A-A' of fig. 2B. Fig. 2D is a schematic cross-sectional view taken along line B-B' of fig. 2B. Fig. 3A is a schematic block diagram of a Metal Oxide Semiconductor Capacitor (MOSCAP) of an integrated circuit device according to some embodiments. Fig. 3B is a schematic plan view of an integrated circuit device according to some embodiments. Fig. 3C is a schematic cross-sectional view taken along line B-B' of fig. 3B. Fig. 3D is a schematic cross-sectional view taken along line C-C' of fig. 3B. Fig. 3E is a schematic cross-sectional view taken along line D-D' of fig. 3B. Fig. 3F is a schematic plan view of a front side Metal Oxide Metal Capacitor (MOMCAP) according to some embodiments. Fig. 3G is a schematic plan view of an integrated circuit device including the front side MOMCAP of fig. 3F, according to some embodiments. Fig. 3H is a schematic plan view of the backside MOMCAP according to some embodiments. Fig. 3I is a schematic plan view of an integrated circuit device including the backside MOMCAP of fig. 3H, according to some embodiments. Fig. 3J is a schematic circ