CN-122002890-A - Anti-irradiation GaN logic circuit structure and manufacturing method thereof

CN122002890ACN 122002890 ACN122002890 ACN 122002890ACN-122002890-A

Abstract

The invention provides an anti-irradiation GaN logic circuit structure and a manufacturing method thereof, and belongs to the technical field of semiconductors. The circuit structure comprises a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization induced hole transport layer, a gallium nitride channel layer and a barrier layer which are arranged from bottom to top, wherein a 2DEG resistance region and an enhanced Schottky grid GaN HEMT region are electrically connected on the device, drain ohmic electrodes, grid electrodes, source ohmic electrodes and HEMT side deep groove electrodes are arranged on the surface of the enhanced Schottky grid GaN HEMT region at intervals along the source-drain direction, a resistance side deep groove electrode connected with the gallium nitride buffer layer is arranged on the surface of the 2DEG resistance region, and the resistance side deep groove electrode and the HEMT side deep groove electrode are bridged. The accumulation of holes at the bottom of the active region can be effectively prevented, threshold drift and fluctuation of the 2DEG resistance caused by the back gate effect are relieved, and the resistance of the device to single particle burning is improved.

Inventors

ZHOU FENG
WANG XIANGYU
LU HAI
XU WEIZONG
ZHOU DONG
REN FANGFANG

Assignees

南京大学

Dates

Publication Date: 20260508
Application Date: 20260410

Claims (10)

1. The utility model provides a radiation-resistant GaN logic circuit structure, its characterized in that includes substrate layer (1), aluminium nitride nucleation layer (2), gallium nitride buffer layer (3), aluminium gallium nitrogen polarization induced hole transport layer (4), gallium nitride channel layer (5) and barrier layer (6) that set up from bottom to top, the circuit structure is last to have along source-drain direction interval arrangement and insulating isolation's 2DEG resistive region (61) and enhancement type Schottky grid GaN HEMT district (62), 2DEG resistive region (61) with enhancement type Schottky grid GaN HEMT district (62) electricity is connected, be provided with the interval arrangement along source-drain direction at enhancement type Schottky grid GaN HEMT district (62) surface, and gradually keep away from 2DEG resistive region (61) drain ohmic electrode (7), grid (8), source ohmic electrode (9) and HEMT side deep groove electrode (10), drain ohmic electrode (7) and source ohmic electrode (9) are connected with gallium nitride channel layer (5), grid (8) are with barrier layer (6) are connected with HEMT (3), HEMT (3) side resistive region (11) are connected with HEMT side deep groove (3), the resistance-side deep trench electrode (11) and the HEMT-side deep trench electrode (10) are bridged.
2. The radiation-resistant GaN logic circuit structure according to claim 1, characterized in that said algan polarization induced hole transport layer (4) is an algan layer, said algan polarization induced hole transport layer (4) having a linearly decreasing aluminum composition in a direction approaching said GaN channel layer (5) from said GaN buffer layer (3).
3. The radiation-resistant GaN logic circuit structure according to claim 1, characterized in that a full isolation region (63) formed by implanting high-energy ions is provided between the 2DEG resistance region (61) and the enhancement schottky gate GaN HEMT region (62), the full isolation region (63) extending longitudinally into the gallium nitride buffer layer (3).
4. A radiation-resistant GaN logic circuit structure as claimed in claim 3, characterized in that said resistance-side deep trench electrode (11) bridging said HEMT-side deep trench electrode (10) is provided in plural, a plurality of said resistance-side deep trench electrodes (11) being arranged at intervals in a direction perpendicular to the source-drain direction.
5. The radiation-resistant GaN logic circuit structure according to claim 4, characterized in that said 2DEG resistive region (61) is divided into an active region (612) and a plurality of field regions (613) by a high-resistance isolation region (611) formed by implanting high-energy ions, said high-resistance isolation region (611) extends in a source-drain direction and longitudinally into said gallium nitride channel layer (5), one end of said active region (612) away from said enhancement schottky gate GaN HEMT region (62) is provided with a resistive high-voltage electrode (12) connected to said gallium nitride channel layer (5), one end of said active region (612) near said enhancement schottky gate GaN HEMT region (62) is provided with a resistive output electrode (13) connected to said gallium nitride channel layer (5), said resistive output electrode (13) bridges said drain ohmic electrode (7), and a plurality of said resistive side deep-trench electrodes (11) are correspondingly disposed in said plurality of field regions (613).
6. The radiation-resistant GaN logic circuit structure according to claim 5, wherein said 2DEG resistive region (61) comprises said active region (612) and two of said field regions (613) symmetrically disposed on both sides of said active region (612) in a direction perpendicular to a source-drain direction, said resistive-side deep trench electrode (11) being disposed at an end of said field region (613) close to said active region (612).
7. The radiation-resistant GaN logic circuit structure of claim 5, characterized in that said resistive high-voltage electrode (12) comprises a first ohmic metal layer (121), a first interconnect metal layer (122) and a first top metal layer (123) arranged from bottom to top, said resistive output electrode (13) comprises a second ohmic metal layer (131), a second interconnect metal layer (132) and a second top metal layer (133) arranged from bottom to top, said drain ohmic electrode (7) comprises a third ohmic metal layer (71) and a third interconnect metal layer (72) arranged from bottom to top, said second interconnect metal layer (132) and said third interconnect metal layer (72) being bridged by a first interconnect metal pillar (14).
8. The radiation-resistant GaN logic circuit structure as claimed in claim 7, wherein the resistive side deep trench electrode (11) comprises a fourth ohmic metal layer (111) and a fourth interconnection metal layer (112) arranged from bottom to top, the HEMT side deep trench electrode (10) comprises a fifth ohmic metal layer (101), a fifth interconnection metal layer (102) and a fifth top metal layer (103) arranged from bottom to top, the fourth interconnection metal layer (112) is bridged with the fifth interconnection metal layer (102) by a second interconnection metal pillar (15), the gate electrode (8) comprises a P-type gallium nitride strip (81) arranged from bottom to top, a schottky metal layer (82), two gate interconnection metal pillars (83) arranged at both ends of the schottky metal layer (82) perpendicular to a source-drain direction, and a gate top metal layer (84) above the gate interconnection metal pillars (83), the source ohmic electrode (9) comprises a source ohmic metal layer (91) arranged from bottom to top, two top source interconnection metal pillars (93) arranged at both ends of the source ohmic metal layer (91) perpendicular to the source-drain direction, the second interconnection metal posts (15) are arranged between the two grid interconnection metal posts (83) and the two source interconnection metal posts (92) in a penetrating mode.
9. The radiation-resistant GaN logic circuit structure according to any of claims 1 to 8, characterized in that the thickness of said aluminum nitride nucleation layer (2) ranges from 15nm to 25nm, the thickness of said gallium nitride buffer layer (3) ranges from 2 μm to 3 μm, the thickness of said aluminum gallium nitride polarization-induced hole transport layer (4) ranges from 100nm to 150nm, the thickness of said gallium nitride channel layer (5) ranges from 200nm to 300nm, and the thickness of said barrier layer (6) ranges from 20nm to 25nm.
10. A method of fabricating the radiation-resistant GaN logic circuit structure of claim 8, comprising: Step 1, sequentially growing a substrate layer (1), an aluminum nitride nucleation layer (2), a gallium nitride buffer layer (3), an aluminum gallium nitride polarization induced hole transport layer (4), a gallium nitride channel layer (5), a barrier layer (6) and a P-type gallium nitride layer on an epitaxial wafer from bottom to top, and removing the P-type gallium nitride layer in a non-pattern area through etching to form a P-type gallium nitride strip (81) in a grid area; Step 2, injecting high-energy ions into the delimited area, controlling the injection depth to penetrate through the AlGaN polarization induced hole transport layer (4) and reach the inside of the GaN buffer layer (3), and forming a full isolation area (63) for completely cutting off electron and hole channels so as to separate a 2DEG resistance area (61) and an enhanced Schottky grid GaN HEMT area (62); Step 3, implanting high-energy ions into the 2DEG resistor region (61), controlling the implantation depth to penetrate through the barrier layer (6) and reach the gallium nitride channel layer (5), and forming a high-resistance isolation region (611) to separate an active region (612) and two field regions (613) symmetrically arranged on two sides of the active region (612) along the direction perpendicular to the source-drain direction; Step 4, growing a dielectric layer on the epitaxial wafer, and respectively forming a shallow contact hole and a deep groove hole by adopting a twice etching process, wherein shallow holes are formed by etching at two ends of the active region (612) along the source-drain direction and the enhanced Schottky grid GaN HEMT region (62) to the interface of the gallium nitride channel layer (5), and deep groove holes penetrating to the gallium nitride buffer layer (3) are etched at the outer side of the high-resistance isolation region (611) of the active region (612) close to two sides of the field region (613) and at one side of the enhanced Schottky grid GaN HEMT region (62) far away from the 2DEG resistor region (61) for the second time, and a resistor high-voltage electrode (12), a resistor output electrode (13), a drain ohmic electrode (7), a source ohmic electrode (9), a resistor side deep groove electrode (11) and a HEMT side deep groove electrode (10) are formed by depositing an ohmic metal layer and performing high-temperature annealing; Step 5, growing the dielectric layer again, and etching and depositing a Schottky metal layer (82) above the P-type gallium nitride strips (81) to form a grid electrode (8); Step 6, regrowing the dielectric layer, wherein interconnection metal is etched and deposited above the resistor high-voltage electrode (12), the resistor output electrode (13), the drain ohmic electrode (7), the grid electrode (8), the source ohmic electrode (9), the resistor side deep groove electrode (11) and the HEMT side deep groove electrode (10) so as to realize bridging of the resistor side deep groove electrode (11) and the HEMT side deep groove electrode (10) and bridging of the resistor output electrode (13) and the drain ohmic electrode (7); And 7, regrowing the dielectric layer, etching and depositing thick metal aluminum above the resistor high-voltage electrode (12), the resistor output electrode (13), the grid electrode (8), the source ohmic electrode (9) and the HEMT side deep groove electrode (10) to serve as top metal, and forming a top metal bonding pad by a photoetching stripping method, wherein the top metal bonding pad is used for leading out all signal ports of a circuit structure and final ports of a hole leading-out network.

Description

Anti-irradiation GaN logic circuit structure and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to an anti-radiation GaN logic circuit structure and a manufacturing method thereof. Background Gallium nitride is used as the core representative of the third generation wide bandgap semiconductor, and has wide application prospect by virtue of the characteristics of high breakdown electric field, high electron saturation drift speed, high temperature resistance, radiation resistance and the like. The resistor-transistor logic (RTL) inverter is used as a basic logic unit for constructing the full gallium nitride power integrated circuit, has the advantages of simple circuit structure, high switching speed, high integration density and the like, and can meet the stringent requirements of aerospace chips on high energy efficiency and light weight. The existing gallium nitride RTL inverter usually adopts a monolithic integration process and is composed of a two-dimensional electron gas (2 DEG) resistor and an enhanced gallium nitride high electron mobility transistor (GaN HEMT) driving tube. The typical structure is based on an insulating substrate such as sapphire or silicon carbide, an AlGaN/GaN heterojunction is formed through epitaxial growth, and high-concentration two-dimensional electron gas is generated by utilizing spontaneous polarization and piezoelectric polarization effects. The enhancement GaN HEMT generally adopts a p-GaN gate structure to realize normally-off characteristic, and the 2DEG resistor forms a determined resistance value through etching interruption or field plate modulation. The two are interconnected through ohmic contact to form a basic logic inversion unit. However, when the GaN RTL inverter operates in a space intense irradiation environment, the single particle irradiation effect seriously threatens the reliability thereof. The high-energy particles are incident on transient electron-hole pairs excited in the device body, and holes are easy to accumulate at the buffer layer and the heterojunction interface due to extremely low mobility and lack of effective dissipation channels. On one hand, for the enhancement GaN HEMT, excessive holes are accumulated on the interface of a buffer layer below a p-GaN grid electrode to generate a positive back grid effect, so that the threshold voltage is negatively floated and even the device is burnt, and on the other hand, for a 2DEG resistor, hole charges accumulated in the deep layer of the substrate can modulate the electron concentration of a channel above the substrate through electrostatic coupling, so that the resistance value is suddenly reduced, and the logic swing and the noise margin of an inverter are damaged. Currently, the existing anti-irradiation reinforcement technology mainly focuses on structural improvement of a single transistor, and lacks a system-level reinforcement scheme for a resistor-transistor integrated logic unit. In particular, monolithic integrated circuits based on insulating substrates such as sapphire and the like have a problem of deep charge accumulation, which has become a key bottleneck restricting aerospace application of GaN logic circuits, because of the lack of a longitudinal charge drain channel, the requirement of hole drain rate cannot be met only by grounding a surface electrode under extremely high dose irradiation. Disclosure of Invention The embodiment of the invention provides an anti-irradiation GaN logic circuit structure and a manufacturing method thereof. The accumulation of holes at the bottom of the active region can be effectively prevented, threshold drift and fluctuation of the 2DEG resistance caused by the back gate effect are relieved, and the resistance of the device to single particle burning is improved. The technical scheme is as follows: In a first aspect, an embodiment of the present invention provides an irradiation-resistant GaN logic circuit structure, including a substrate layer, an aluminum nitride nucleation layer, a gallium nitride buffer layer, an aluminum gallium nitride polarization induced hole transport layer, a gallium nitride channel layer, and a barrier layer disposed from bottom to top, where the circuit structure is provided with a 2DEG resistive region and an enhanced schottky gate GaN HEMT region that are disposed at intervals along a source-drain direction and insulated and isolated, the 2DEG resistive region is electrically connected with the enhanced schottky gate GaN HEMT region, a drain ohmic electrode, a gate electrode, a source ohmic electrode, and a HEMT side deep trench electrode disposed at intervals along the source-drain direction and gradually far from the 2DEG resistive region, the drain ohmic electrode and the source ohmic electrode are connected with the gallium nitride channel layer, the gate electrode is connected with the barrier layer, and the HEMT side deep trench el