CN-122002891-A - SOI-based GaN concave gate half-bridge integrated device and preparation method thereof

CN122002891ACN 122002891 ACN122002891 ACN 122002891ACN-122002891-A

Abstract

The invention relates to an SOI (silicon on insulator) -based GaN concave gate half-bridge integrated device and a preparation method thereof, wherein the SOI substrate, an AlN layer, a GaN layer, an AlGaN layer and a second insulating medium layer are sequentially arranged from bottom to top, the SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon, the second insulating medium layer is etched, source metal and drain metal are grown, deep grooves below the source are etched and penetrate through the second insulating medium layer to the AlN layer, the second insulating medium layer and part of AlGaN layer in a concave gate area are etched, gate metal is grown after the gate insulating medium is grown to form a gate, field plate metal is grown above the source metal and the gate metal and fills the third insulating medium layer, deep grooves are arranged in the middle of the device and penetrate through the third insulating medium layer to the top silicon and fill insulating medium, a fourth insulating medium layer is filled at the top of the device, and the half-bridge integrated device is obtained through a top through hole and an interconnection process.

Inventors

ZHENG LI
FENG WENYAO
CHENG XINHONG
Zhou Xuetong

Assignees

中国科学院上海微系统与信息技术研究所

Dates

Publication Date: 20260508
Application Date: 20241031

Claims (8)

1. The SOI-based GaN concave gate half-bridge integrated device is characterized by comprising an SOI substrate, an AlN layer (4), a GaN layer (5), an AlGaN layer (6) and a second insulating medium layer (7) which are sequentially arranged from bottom to top, wherein the SOI substrate comprises a substrate silicon (1), a first insulating medium layer (2) and a top silicon (3), the second insulating medium layer (7) is etched, a source metal (8) and a drain metal (9) are grown, deep groove etching is conducted below the source, the second insulating medium layer (7) penetrates through the AlN layer (4), the second insulating medium layer (7) and a part of AlGaN layer (6) in a concave gate area are etched, a gate metal (11) is grown after the second insulating medium layer (7) and a part of AlGaN layer (6) are etched, a gate is formed, a field plate metal (12) is grown above the source metal (8) and the gate metal (11), a third insulating medium layer (13) is filled, a deep groove penetrating through the third insulating medium layer (13) to the top silicon (3) is arranged in the middle of the half-bridge integrated device, insulating medium is filled in the groove, and the top of the deep groove is filled, and the deep groove is formed in the groove, and the deep groove is formed, and the deep groove is used for interconnecting the gate insulating medium layer (14, and the deep groove is formed, and the deep groove and the top insulating layer is formed, and the gate insulating layer.
2. The SOI-based GaN recessed gate half-bridge integrated device of claim 1, wherein the source metal (8) and drain metal (9) comprise one or more of W, tiN, al, ni, ti, au, mo or Pt.
3. The SOI-based GaN recessed gate half-bridge integrated device of claim 1, wherein the gate metal (10) comprises one or more of W, tiN, al, ni, ti, au, mo or Pt.
4. The SOI-based GaN recessed gate half-bridge integrated device of claim 1 wherein the insulating medium comprises one or more of SiO 2 、Al 2 O 3 、HfO 2 、La 2 O 3 、ZrO 2 or Si 3 N 4 stacked structures.
5. A method of fabricating an SOI-based GaN recessed gate half-bridge integrated device as recited in any one of claims 1-4 comprising: An AlN layer (4), a GaN layer (5), an AlGaN layer (6) and a second insulating medium layer (7) are sequentially grown on an SOI substrate by utilizing an SOI-based GaN HEMT process to obtain an SOI-based GaN HEMT device, wherein the SOI substrate comprises substrate silicon (1), a first insulating medium layer (2) and top layer silicon (3); (2) Etching the second insulating dielectric layer (7), and growing source metal (8) and drain metal (9), wherein deep groove etching is performed below the source, and the deep groove etching penetrates through the second insulating dielectric layer (7), the AlGaN layer (6), the GaN layer (5) and the AlN layer (4) and is terminated at the top silicon (3); (3) Etching the second insulating dielectric layer (7) and part of AlGaN layer (6) of the concave gate region, growing gate metal (11) after growing the gate insulating dielectric (10) to form a gate; (4) Growing a field plate metal (12) above the source metal (8) and the gate metal (11) and filling a third insulating dielectric layer (13); (5) Deep groove etching is carried out in the middle of the device, and the deep groove etching penetrates through the third insulating dielectric layer (13), the second insulating dielectric layer (7), the AlGaN layer (6), the GaN layer (5), the AlN layer (4) and the top silicon (3) and is terminated at the first insulating dielectric layer (2); (6) Filling a deep groove in the middle of the device with an insulating medium to realize isolation of the two sides of the high side and the low side of the device; (7) Filling a fourth insulating medium layer (14) on the top of the device; (8) And connecting the high-side source electrode and the low-side drain electrode on two sides of the deep groove of the device through the top through hole and the interconnection process, and respectively leading out the low-side source electrode and the high-side drain electrode of the device to obtain the SOI-based GaN concave gate half-bridge integrated device.
6. The method of fabricating a GaN recessed gate half-bridge integrated device on an SOI substrate according to claim 5, wherein the growth of the insulating medium in steps (1), (3), (4), (6), (7) comprises chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, sputtering.
7. The method of fabricating a SOI-based GaN recessed gate half-bridge integrated device as defined in claim 5, wherein the etching method in steps (2), (3), (5) comprises ICP or RIE, and the etching atmosphere comprises one or more of SF 6 、CHF 3 、BCl 3 、CF 4 、C 4 F 8 、Cl 2 or He.
8. The method of fabricating a SOI-based GaN recessed gate half-bridge integrated device as defined in claim 5 wherein the metal growth methods in steps (2), (3), (4) include magnetron sputtering or electron beam evaporation.

Description

SOI-based GaN concave gate half-bridge integrated device and preparation method thereof Technical Field The invention belongs to the field of integrated circuits, and particularly relates to an SOI (silicon on insulator) -based GaN concave gate half-bridge integrated device and a preparation method thereof. Background With the development of power semiconductor devices, power devices manufactured from wide bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC) are becoming more and more widely used. GaN-based power devices, particularly heterojunction (e.g., alGaN/GaN) with high mobility two-dimensional electron gas (2 DEG) channel, have become candidates for new generation power conversion systems with high conversion efficiency and high power density due to excellent material characteristics such as wide forbidden band, large critical breakdown field strength, and high operating temperature. In semiconductor devices, SOI (Silicon On Insulator ) technology is becoming one of the key technologies for improving integrated circuit performance due to its superior electrical isolation, low parasitic capacitance, and high radiation resistance. Conventional half-bridge circuits typically use MOSFETs as switching devices. However, with the increase in power density and the increase in operating frequency, conventional MOSFET devices face challenges such as high switching losses, high leakage currents, and switching speed limitations due to capacitive effects. Therefore, the GaN HEMT device can effectively solve the problems, and provides better switching performance and energy efficiency. The concave gate HEMT structure can realize an enhanced device and control the threshold voltage more accurately, and the half-bridge integration technology can have remarkable advantages in the fields of power electronics and the like, and particularly has outstanding aspects of improving efficiency, reducing circuit volume and reducing cost. Through SOI base concave gate HEMT half-bridge integration, the low leakage current and high voltage resistance of SOI technology can be fully exerted, the switching loss is reduced, and meanwhile, the power density and the thermal efficiency of the system are improved. Disclosure of Invention The invention aims to provide an SOI (silicon on insulator) -based GaN concave gate half-bridge integrated device and a preparation method thereof, so as to improve the power density and efficiency of a system, reduce the switching loss and reduce parasitic parameters. The invention provides an SOI-based GaN concave gate half-bridge integrated device, which comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer and a second insulating medium layer which are sequentially arranged from bottom to top, wherein the SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon, the second insulating medium layer is etched, source metal and drain metal are grown under the source, deep groove etching is carried out to penetrate through the second insulating medium layer to the AlN layer, the second insulating medium layer and part of AlGaN layer in a concave gate area are etched, gate metal is grown after the gate insulating medium is grown to form a gate, a field plate metal is grown above the source metal and the gate metal and is filled with the third insulating medium layer, a deep groove is arranged in the middle of the half-bridge integrated device and penetrates through the third insulating medium layer to the top silicon, insulating medium is filled in the deep groove, a fourth insulating medium layer is filled at the top of the device, and the SOI-based concave gate half-bridge integrated device is obtained through a top through hole and an interconnection process. Preferably, the source metal and the drain metal include one or more of W, tiN, al, ni, ti, au, mo or Pt. Preferably, the gate metal comprises one or more of W, tiN, al, ni, ti, au, mo or Pt. Preferably, the insulating medium comprises one or more of SiO 2、Al2O3、HfO2、La2O3、ZrO2 or Si 3N4. The invention also provides a preparation method of the SOI-based GaN concave gate half-bridge integrated device, which comprises the following steps: (1) Sequentially growing an AlN layer, a GaN layer, an AlGaN layer and a second insulating medium layer on an SOI substrate by utilizing an SOI-based GaN HEMT process to obtain an SOI-based GaN HEMT device, wherein the SOI substrate comprises substrate silicon, a first insulating medium layer and top layer silicon; (2) Etching the second insulating dielectric layer, growing source metal and drain metal, wherein deep groove etching is performed below the source, and the second insulating dielectric layer, the AlGaN layer, the GaN layer and the AlN layer penetrate through and terminate at the top silicon; (3) Etching the second insulating dielectric layer and part of AlGaN layer of the concave gate region, growing gate metal after gr