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CN-122002892-A - SOI-based MIS p-GaN HEMT half-bridge integrated circuit and preparation method thereof

CN122002892ACN 122002892 ACN122002892 ACN 122002892ACN-122002892-A

Abstract

The invention relates to an SOI-based MIS p-GaN HEMT half-bridge integrated circuit and a preparation method thereof, wherein the SOI-based MIS p-GaN HEMT half-bridge integrated circuit comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer, a p-GaN layer and a second insulating medium layer which are sequentially arranged from bottom to top; the SOI substrate comprises substrate silicon, a first insulating medium layer and a top silicon, a p-GaN layer and a second insulating medium layer are etched, a third insulating medium layer is grown to prepare a grid electrode, source electrode metal and drain electrode metal are respectively grown on two sides of the grid electrode, field plate metal is grown above the source electrode metal and the grid electrode metal and is filled with a fourth insulating medium layer, a deep groove is arranged in the middle of a circuit and penetrates through the fourth insulating medium layer, the third insulating medium layer, the AlGaN layer, the GaN layer, the AlN layer and the top silicon to be filled with insulating mediums, a fifth insulating medium layer is filled at the top, and a half-bridge integrated circuit is obtained through a top through hole and an interconnection process. The invention can reduce parasitic effect, leakage current and switching loss.

Inventors

  • ZHENG LI
  • FENG WENYAO
  • CHENG XINHONG
  • Zhou Xuetong

Assignees

  • 中国科学院上海微系统与信息技术研究所

Dates

Publication Date
20260508
Application Date
20241031

Claims (8)

  1. 1. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit is characterized by comprising an SOI substrate, an AlN layer (4), a GaN layer (5), an AlGaN layer (6), a p-GaN layer (7) and a second insulating medium layer (8) which are sequentially arranged from bottom to top, wherein the SOI substrate comprises a substrate silicon (1), a first insulating medium layer (2) and a top silicon (3), the second insulating medium layer (8) of the p-GaN layer (7) and the corresponding region outside a grid region is etched, a third insulating medium layer (9) is filled, a grid metal (10) is then grown to obtain a grid, source metal (11) and drain metal (12) are respectively grown on two sides of the grid region of the p-GaN layer (7), a field plate metal (13) is grown above the source metal (11) and the grid metal (10) and is filled with the fourth insulating medium layer (14), a deep groove penetrating through the fourth insulating medium layer (14), the third insulating medium layer (9), the layer (6), the layer (5) and the GaN layer (4) and the top silicon layer (3) are filled in the middle of the half-bridge integrated circuit, and the top of the half-bridge integrated circuit is filled with the deep groove penetrates through the fourth insulating medium layer (14), the third insulating medium layer (4) and the top layer and the top silicon-insulating medium layer is filled with the top-insulating medium layer, the top-layer and the top-layer-insulating medium layer-insulating half-HEMT half-bridge HEMT.
  2. 2. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit of claim 1, wherein the insulating medium comprises one or more stacked structures of SiO 2 、Al 2 O 3 、HfO 2 、La 2 O 3 、ZrO 2 、Si 3 N 4 .
  3. 3. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit of claim 1, wherein the gate metal (10) comprises one or more of W, tiN, al, ni, ti, au, mo, pt.
  4. 4. The SOI-based MIS p-GaN HEMT half-bridge integrated circuit of claim 1, wherein the source metal (9) and drain metal (10) comprise one or more of W, tiN, al, ni, ti, au, mo, pt.
  5. 5. A method of manufacturing the SOI-based MIS p-GaN HEMT half-bridge integrated circuit of any one of claims 1-4, comprising: An AlN layer (4), a GaN layer (5), an AlGaN layer (6), a p-GaN layer (7) and a second insulating medium layer (8) are sequentially grown on an SOI substrate by utilizing an SOI-based GaN HEMT process to obtain a p-GaN HEMT structure, wherein the SOI substrate comprises substrate silicon (1), a first insulating medium layer (2) and top layer silicon (3); (2) Etching the p-GaN layer (7) outside the grid region and the second insulating medium layer (8) in the corresponding region, filling the third insulating medium layer (9), and then growing grid metal (10) to obtain a grid, so as to form an MIS p-GaN structure; (3) Growing source metal (11) and drain metal (12) on two sides of a grid region of the p-GaN layer (7), wherein deep groove etching is used below the source electrode, penetrates through the third insulating dielectric layer (9), the AlGaN layer (6), the GaN layer (5) and the AlN layer (4) and is terminated at the top silicon (3); (4) Growing a field plate metal (13) over the source metal (11) and the gate metal (10) and filling a fourth insulating dielectric layer (14); (5) Deep groove etching is carried out in the middle of the circuit, and the deep groove etching penetrates through the fourth insulating medium layer (14), the third insulating medium layer (9), the AlGaN layer (6), the GaN layer (5), the AlN layer (4) and the top silicon (3) and is terminated at the first insulating medium layer (2); (6) Filling a deep groove in the middle of the circuit with an insulating medium to realize isolation of the two sides of the high side and the low side of the circuit; (7) Filling a fifth insulating medium layer (15) on the top of the circuit; (8) And connecting the high-side source electrode and the low-side drain electrode on two sides of the deep groove of the device through the top through hole and the interconnection process, and respectively leading out the low-side source electrode and the high-side drain electrode of the device to obtain the SOI-based MIS p-GaN HEMT half-bridge integrated circuit.
  6. 6. The method of claim 5, wherein the method of growing the insulating medium in steps (1), (2), (4), (6), (7) comprises one or more of chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, thermal or electron beam evaporation, sputtering.
  7. 7. The method of manufacturing a SOI-based MIS p-GaN HEMT half-bridge integrated circuit according to claim 5, wherein the etching method in steps (2), (3), (5) comprises ICP or RIE, and the etching atmosphere comprises one or more of SF 6 、CHF 3 、BCl 3 、CF 4 、C 4 F 8 、Cl 2 , he.
  8. 8. The method of manufacturing a SOI-based MIS p-GaN HEMT half-bridge integrated device of claim 5, wherein the metal growth methods in steps (2), (3), (4) include magnetron sputtering or electron beam evaporation.

Description

SOI-based MIS p-GaN HEMT half-bridge integrated circuit and preparation method thereof Technical Field The invention belongs to the field of microelectronics and solid electronics, and particularly relates to an SOI (silicon on insulator) -based MIS (MIS) p-GaN HEMT (high Electron mobility transistor) half-bridge integrated circuit and a preparation method thereof. Background With the development of power semiconductor devices, power devices manufactured from wide bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide (SiC) are becoming more and more widely used. GaN-based power devices, particularly heterojunction (e.g., alGaN/GaN) with high mobility two-dimensional electron gas (2 DEG) channel, have become candidates for new generation power conversion systems with high conversion efficiency and high power density due to excellent material characteristics such as wide forbidden band, large critical breakdown field strength, and high operating temperature. In semiconductor devices, SOI (Silicon On Insulator ) technology is becoming one of the key technologies for improving integrated circuit performance due to its superior electrical isolation, low parasitic capacitance, and high radiation resistance. Conventional half-bridge circuits typically use MOSFETs as switching devices. However, with the increase in power density and the increase in operating frequency, conventional MOSFET devices face challenges such as high switching losses, high leakage currents, and switching speed limitations due to capacitive effects. Therefore, the GaN HEMT device can effectively solve the problems, and provides better switching performance and energy efficiency. The MIS p-GaN HEMT structure can realize an enhanced device and simultaneously reduce gate leakage current, has good thermal stability, and the half-bridge integration technology can have remarkable advantages in the fields of power electronics and the like, and particularly has outstanding aspects of improving efficiency, reducing circuit volume and reducing cost. Through SOI base concave gate HEMT half-bridge integration, the low leakage current and high voltage resistance of SOI technology can be fully exerted, the switching loss is reduced, and meanwhile, the power density and the thermal efficiency of the system are improved. Disclosure of Invention The invention aims to provide an SOI-based MIS p-GaN HEMT half-bridge integrated circuit and a preparation method thereof, so as to realize a monolithic integrated half-bridge circuit and reduce switching loss and gate leakage. The invention provides an SOI-based MIS p-GaN HEMT half-bridge integrated circuit, which comprises an SOI substrate, an AlN layer, a GaN layer, an AlGaN layer, a p-GaN layer and a second insulating medium layer which are sequentially arranged from bottom to top, wherein the SOI substrate comprises substrate silicon, a first insulating medium layer and top silicon, the second insulating medium layer of the p-GaN layer and a corresponding area outside a grid area is etched to fill a third insulating medium layer, grid metal is then grown to obtain a grid, source metal and drain metal are respectively grown on two sides of the grid area of the p-GaN layer, field plate metal is grown above the source metal and the grid metal and is filled with a fourth insulating medium layer, a deep groove is formed in the middle of the half-bridge integrated circuit and penetrates through the fourth insulating medium layer, the third insulating medium layer, the AlGaN layer, the AlN layer and top silicon, the fifth insulating medium layer is filled in the deep groove, and the SOI-based MIS p-GaN half-bridge integrated circuit is obtained through a top through hole and an interconnection process. Preferably, the insulating medium comprises one or more stacked structures of SiO2、Al2O3、HfO2、La2O3、ZrO2、Si3N4. Preferably, the gate metal comprises one or more of W, tiN, al, ni, ti, au, mo, pt. Preferably, the source metal and the drain metal include one or more of W, tiN, al, ni, ti, au, mo, pt. The invention also provides a preparation method of the SOI-based MIS p-GaN HEMT half-bridge integrated circuit, which comprises the following steps: (1) Sequentially growing an AlN layer, a GaN layer, an AlGaN layer, a p-GaN layer and a second insulating medium layer on an SOI substrate by utilizing an SOI-based GaN HEMT process to obtain a p-GaN HEMT structure, wherein the SOI substrate comprises substrate silicon, a first insulating medium layer and top layer silicon; (2) Etching the p-GaN layer outside the grid region and the second insulating medium layer in the corresponding region, filling the third insulating medium layer, and then growing grid metal to obtain a grid, so as to form an MIS p-GaN structure; (3) Growing source metal and drain metal on the side of the grid region of the p-GaN layer, wherein deep groove etching is used below the source electrode, penetrates through the third insu