CN-122002893-A - Monolithic integrated GaN HEMT and Si MOS double-gate bidirectional switch capode and preparation method thereof

CN122002893ACN 122002893 ACN122002893 ACN 122002893ACN-122002893-A

Abstract

The invention discloses a monolithic integrated GaN HEMT and Si MOS double-gate bidirectional switch cam and a preparation method thereof, relating to the technical field of semiconductors. The double-gate GaN HEMT is provided with a first gate and a second gate, and is positioned between the source and the drain. The source and the drain of the two Si MOS are respectively connected with the gate and the source/drain of the GaN HEMT through metals to form a cathode configuration. The invention combines the low on-resistance and quick switching characteristics of the high-voltage GaN HEMT with the advantages of easy driving and high reliability of the low-voltage Si MOS, realizes the high-performance enhanced double-gate bidirectional switch through monolithic integration, and effectively solves the problems of large on-resistance, high static power consumption, complex driving, large process difficulty and the like in the traditional scheme.

Inventors

SONG XIUFENG
TANG JIACHEN
ZHAO SHENGLEI
SUN XUEJING
DU YIHANG
YU LONGYANG
ZHANG JINCHENG
HAO YUE

Assignees

西安电子科技大学

Dates

Publication Date: 20260508
Application Date: 20251217

Claims (10)

1. A monolithic integrated GaN HEMT and Si MOS double-gate bidirectional switch capode is characterized by comprising a substrate, and a double-gate GaN HEMT, a first Si MOS and a second Si MOS which are integrated on the substrate, Passivation layers are arranged among the first Si MOS, the double-gate GaN HEMT and the second Si MOS and on the upper surfaces of the first Si MOS, the double-gate GaN HEMT and the second Si MOS; and the double-gate GaN HEMT is connected with the first Si MOS and the second Si MOS to form a cathode.
2. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch cam of claim 1, The double-gate GaN HEMT is positioned between the first Si MOS and the second Si MOS; The source electrode of the first Si MOS is in metal interconnection with the first grid electrode of the double-grid GaN HEMT, and the drain electrode of the first Si MOS is in metal interconnection with the source electrode of the double-grid GaN HEMT; The source electrode of the second Si MOS is connected with the second grid electrode of the double-grid GaN HEMT through metal, and the drain electrode of the second Si MOS is connected with the drain electrode of the double-grid GaN HEMT through metal.
3. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch cam of claim 1, wherein said substrate comprises a Si substrate, a GaN substrate, a sapphire substrate, or a SiC substrate.
4. The monolithically integrated GaN HEMT and Si MOS dual gate bidirectional switch cam of claim 1, wherein said first Si MOS and said second Si MOS each comprise a P-type silicon semiconductor epitaxial region on said substrate, a first n+ source region and a second n+ source region are disposed in between said P-type silicon semiconductor epitaxial region, a source of Si MOS is disposed on said first n+ source region, a drain of Si MOS is disposed on said second n+ source region, and a gate of Si MOS is disposed on said P-type silicon semiconductor epitaxial region between said drain of Si MOS and said source of Si MOS.
5. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch castode of claim 1, wherein the dual gate GaN HEMT comprises a nucleation layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially from bottom to top on the substrate, the barrier layer having a source, a first gate, a second gate, and a drain of the dual gate GaN HEMT disposed thereon, wherein the first gate of the dual gate GaN HEMT is located between the source and the drain thereof, and the second gate of the dual gate GaN HEMT is located between the first gate and the drain thereof.
6. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch cam of claim 5, wherein the nucleation layer material comprises AlN or AlGaN with a thickness of 30-500 μm.
7. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch cam of claim 5, wherein the buffer layer material comprises GaN, alN or AlGaN with a thickness of 0.5-5 μm.
8. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch cam of claim 5, wherein the material of said channel layer comprises GaN, alN or AlGaN, having a thickness of 50-500nm.
9. The monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch cam of claim 5, wherein the barrier layer is AlGaN with a thickness of 10-50nm.
10. A method for preparing a monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch capode, suitable for use in a monolithically integrated GaN HEMT and Si MOS dual gate bi-directional switch capode according to any one of claims 1-9, the method comprising: Step 1, obtaining an epitaxial wafer, wherein the epitaxial wafer comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially laminated from bottom to top; Step 2, etching the barrier layer, the channel layer, the buffer layer and the nucleation layer on two sides of the epitaxial wafer, and forming Si MOS regions on two sides of the GaN HEMT region; step 3, epitaxially forming a P-type silicon semiconductor epitaxial region on the substrate of the Si MOS region; step 4, forming a first N+ source region and a second N+ source region in the P-type silicon semiconductor epitaxial region by adopting ion implantation; Step 5, preparing ohmic contact metal electrodes on the first N+ source region, the second N+ source region and the barrier layer to form a source electrode and a drain electrode of the Si MOS and a source electrode and a drain electrode of the double-gate GaN HEMT; Step 6, preparing Schottky contact metal electrodes on the P-type silicon semiconductor epitaxial region and the barrier layer between the source electrode and the drain electrode of the double-gate GaN HEMT, and forming a grid electrode of the Si MOS and a first grid electrode and a second grid electrode of the double-gate GaN HEMT; And 7, depositing a passivation layer on the surface of the device by adopting a plasma chemical vapor deposition process, etching the source electrode and the drain electrode of the Si MOS and the passivation layer on the source electrode, the drain electrode, the first grid electrode and the second grid electrode of the double-grid GaN HEMT to form an electrode contact hole, and realizing the connection of the two Si MOS and the cascode of the double-grid GaN HEMT by utilizing metal interconnection through the electrode contact hole.

Description

Monolithic integrated GaN HEMT and Si MOS double-gate bidirectional switch capode and preparation method thereof Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to a monolithic integration GaN HEMT and Si MOS double-gate bidirectional switch cam and a preparation method thereof. Background The bidirectional switch has important roles in electric power applications such as electric automobiles, renewable energy power generation, vehicle-to-vehicle communication, energy storage systems and the like, can efficiently control bidirectional energy flow, and ensures reliable and safe operation of the system. The bidirectional switch based on the monolithic integration technology can realize high power conversion efficiency, gradually becomes an industry standard in the field of power electronics, and is widely applied to scenes such as charging piles, battery energy management systems, uninterruptible Power Supplies (UPS) and the like. Currently, the mainstream technology includes SiC and GaN bidirectional switches, but the structure and performance thereof still need to be further optimized. The technical path for realizing the bidirectional switch at present mainly comprises three steps, namely that a plurality of discrete devices (such as MOSFET) are used for cascading to form the bidirectional switch, but the cascading scheme of the discrete devices can lead to the increase of the system volume, the increase of the on-resistance and the increase of the cost, the depletion type GaN device is adopted, the depletion type GaN device is difficult to meet the scene requirement of low power consumption due to high static power consumption and poor process stability, and the enhancement type GaN bidirectional switch structure based on the p-GaN grid realizes the bidirectional conduction and blocking function through the double-grid design and the common drain electrode area, and the enhancement type GaN device can realize the bidirectional control, but the p-GaN etching process has high precision requirement, high manufacturing difficulty and limited on-current density. In addition, siC bidirectional switches are mostly arranged longitudinally, which has the difficult problem of bidirectional voltage blocking, and it is difficult to combine low on-resistance and fast switching characteristics. Disclosure of Invention In order to solve the problems in the prior art, the invention provides a monolithic integration GaN HEMT and Si MOS double-gate bidirectional switch cathode and a preparation method thereof. The technical problems to be solved by the invention are realized by the following technical scheme: The invention provides a monolithic integrated GaN HEMT and Si MOS double-gate bidirectional switch cathode, which comprises a substrate, and a double-gate GaN HEMT, a first Si MOS and a second Si MOS which are integrated on the substrate, Passivation layers are arranged among the first Si MOS, the double-gate GaN HEMT and the second Si MOS and on the upper surfaces of the first Si MOS, the double-gate GaN HEMT and the second Si MOS; and the double-gate GaN HEMT is connected with the first Si MOS and the second Si MOS to form a cathode. In one embodiment of the invention, the dual gate GaN HEMT is located between the first Si MOS and the second Si MOS; The source electrode of the first Si MOS is in metal interconnection with the first grid electrode of the double-grid GaN HEMT, and the drain electrode of the first Si MOS is in metal interconnection with the source electrode of the double-grid GaN HEMT; The source electrode of the second Si MOS is connected with the second grid electrode of the double-grid GaN HEMT through metal, and the drain electrode of the second Si MOS is connected with the drain electrode of the double-grid GaN HEMT through metal. In one embodiment of the invention, the substrate comprises a Si substrate, a GaN substrate, a sapphire substrate, or a SiC substrate. In one embodiment of the present invention, the first Si MOS and the second Si MOS each include a P-type silicon semiconductor epitaxial region on the substrate, a first n+ source region and a second n+ source region are disposed in the P-type silicon semiconductor epitaxial region, a source of the Si MOS is disposed on the first n+ source region, a drain of the Si MOS is disposed on the second n+ source region, and a gate of the Si MOS is disposed on the P-type silicon semiconductor epitaxial region between the drain of the Si MOS and the source of the Si MOS. In one embodiment of the invention, the dual-gate GaN HEMT comprises a nucleation layer, a buffer layer, a channel layer and a barrier layer which are sequentially stacked on the substrate from bottom to top, wherein the barrier layer is provided with a source electrode, a first grid electrode, a second grid electrode and a drain electrode of the dual-gate GaN HEMT, the first grid electrode of the dual-gate GaN HEMT is posit