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CN-122002894-A - Transistor and manufacturing method thereof

CN122002894ACN 122002894 ACN122002894 ACN 122002894ACN-122002894-A

Abstract

The present disclosure provides a transistor and a method of fabricating the same. The transistor comprises a channel layer, a barrier layer, a first grid electrode, a second grid electrode, a first electrode, a second electrode and a third electrode, wherein the barrier layer is laminated on the channel layer, the first grid electrode and the second grid electrode are located on the barrier layer, the first electrode, the second electrode and the third electrode are respectively inserted into the barrier layer, the first electrode, the first grid electrode, the second grid electrode and the third electrode are sequentially arranged along a first direction a, and the first grid electrode and the second grid electrode are connected in series.

Inventors

  • WANG JUNNAN
  • CHEN KAI
  • GUO LILI
  • SUN JIAN
  • WANG JIANGBO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251223

Claims (10)

  1. 1. A transistor, characterized in that the transistor comprises a channel layer (101), a barrier layer (102), a first gate (103), a second gate (104), a first electrode (105), a second electrode (106) and a third electrode (107); The barrier layer (102) is laminated on the channel layer (101), the first gate electrode (103) and the second gate electrode (104) are positioned on the barrier layer (102), and the first electrode (105), the second electrode (106) and the third electrode (107) are respectively inserted into the barrier layer (102); Along a first direction a, the first electrode (105), the first grid electrode (103), the second electrode (106), the second grid electrode (104) and the third electrode (107) are sequentially arranged; The first gate (103) and the second gate (104) are connected in series.
  2. 2. The transistor according to claim 1, characterized in that the orthographic projection of the first electrode (105) on the channel layer (101) surface and the orthographic projection of the second electrode (106) on the channel layer (101) surface are symmetrical with respect to the orthographic projection of the first gate (103) on the channel layer (101) surface; the orthographic projection of the second electrode (106) on the surface of the channel layer (101) and the orthographic projection of the third electrode (107) on the surface of the channel layer (101) are symmetrical with respect to the orthographic projection of the second gate electrode (104) on the surface of the channel layer (101).
  3. 3. The transistor of claim 1 or 2, further comprising a first field plate structure (191), a second field plate structure (192), a third field plate structure (193) and a fourth field plate structure (194); -the first field plate structure (191) is located between the first electrode (105) and the first gate (103), -the second field plate structure (192) is located between the first gate (103) and the second electrode (106), -the third field plate structure (193) is located between the second electrode (106) and the second gate (104), -the fourth field plate structure (194) is located between the second gate (104) and the third electrode (107); The front projection of the first field plate structure (191) on the surface of the channel layer (101) and the front projection of the second field plate structure (192) on the surface of the channel layer (101) are symmetrical with respect to the front projection of the first gate electrode (103) on the surface of the channel layer (101), and the front projection of the third field plate structure (193) on the surface of the channel layer (101) and the front projection of the fourth field plate structure (194) on the surface of the channel layer (101) are symmetrical with respect to the front projection of the second gate electrode (104) on the surface of the channel layer (101).
  4. 4. A transistor according to claim 3, characterized in that the first field plate structure (191) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107), respectively, the second field plate structure (192) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107), respectively, the third field plate structure (193) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107), respectively, and the fourth field plate structure (194) is insulated from the first electrode (105), the second electrode (106) and the third electrode (107), respectively.
  5. 5. A transistor according to claim 3, characterized in that the transistor further comprises a fifth field plate structure (1111), a sixth field plate structure (1112), a seventh field plate structure (1113) and an eighth field plate structure (1114); One end of the fifth field plate structure (1111) is connected with the second electrode (106), the other end of the fifth field plate structure (1111) is far away from the second electrode (106) along a first direction a, one end of the sixth field plate structure (1112) is connected with the second electrode (106), the other end of the sixth field plate structure (1112) is far away from the second electrode (106) along a direction opposite to the first direction a, one end of the seventh field plate structure (1113) is connected with the second electrode (106), the other end of the seventh field plate structure (1113) is far away from the second electrode (106) along a first direction a, one end of the eighth field plate structure (1114) is connected with the second electrode (106), the other end of the eighth field plate structure (1114) is far away from the second electrode (106) along a direction opposite to the first direction a, and the fifth field plate structure (1111), the sixth field plate structure (1112), the seventh field plate structure (1113) and the eighth field plate structure (1114) are sequentially arranged along a direction perpendicular to the second direction b.
  6. 6. The transistor of claim 5, further comprising a ninth field plate structure (1115) and a tenth field plate structure (1116), wherein one end of the ninth field plate structure (1115) is connected to the first electrode (105), the other end of the fifth field plate structure (1111) is far from the first electrode (105) along a first direction a, one end of the tenth field plate structure (1116) is connected to the first electrode (105), the other end of the tenth field plate structure (1116) is far from the first electrode (105) along the first direction a, and the ninth field plate structure (1115) and the tenth field plate structure (1116) are sequentially arranged along the second direction b.
  7. 7. The transistor of claim 6, wherein the sixth field plate structure (1112) is located between the ninth field plate structure (1115) and the tenth field plate structure (1116), the tenth field plate structure (1116) being located between the sixth field plate structure (1112) and the eighth field plate structure (1114).
  8. 8. The transistor of claim 5, further comprising an eleventh field plate structure (1117) and a twelfth field plate structure (1118), wherein one end of the eleventh field plate structure (1117) is connected to the third electrode (107), the other end of the eleventh field plate structure (1117) is distant from the third electrode (107) along the opposite direction of the first direction a, one end of the twelfth field plate structure (1118) is connected to the third electrode (107), the other end of the twelfth field plate structure (1118) is distant from the third electrode (107) along the opposite direction of the first direction a, and the eleventh field plate structure (1117) and the twelfth field plate structure (1118) are sequentially arranged along the second direction b.
  9. 9. The transistor of claim 8, wherein the eleventh field plate structure (1117) is located between the fifth field plate structure (1111) and the seventh field plate structure (1113), the seventh field plate structure (1113) being located between the eleventh field plate structure (1117) and the twelfth field plate structure (1118).
  10. 10. A method of fabricating a transistor, the method comprising: Sequentially manufacturing a channel layer and a barrier layer, wherein the barrier layer is laminated on the channel layer; manufacturing a first grid electrode and a second grid electrode on the barrier layer, wherein the first grid electrode and the second grid electrode are connected in series; And manufacturing a first electrode, a second electrode and a third electrode, wherein the first electrode, the second electrode and the third electrode are respectively inserted into the barrier layer, and the first electrode, the first grid electrode, the second grid electrode and the third electrode are sequentially arranged along a first direction a.

Description

Transistor and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor devices, and more particularly, to a transistor and a method of fabricating the same. Background GaN-based transistors are candidates for next generation power switching applications due to their excellent device characteristics (low specific on-resistance, low switching loss, and high breakdown voltage). However, how to optimize the performance of transistors is a current challenge. Disclosure of Invention The embodiment of the disclosure provides a transistor and a manufacturing method thereof, which can optimize the performance of the transistor. The technical scheme is as follows: in one aspect, a transistor is provided that includes a channel layer, a barrier layer, a first gate electrode, a second gate electrode, a first electrode, a second electrode, and a third electrode; the barrier layer is laminated on the channel layer, the first gate electrode and the second gate electrode are positioned on the barrier layer, and the first electrode, the second electrode and the third electrode are respectively inserted into the barrier layer; The first electrode, the first grid electrode, the second grid electrode and the third electrode are sequentially arranged along a first direction a; the first gate and the second gate are connected in series. Optionally, the orthographic projection of the first electrode on the channel layer surface and the orthographic projection of the second electrode on the channel layer surface are symmetrical with respect to the orthographic projection of the first gate on the channel layer surface; The orthographic projection of the second electrode on the channel layer surface and the orthographic projection of the third electrode on the channel layer surface are symmetrical with respect to the orthographic projection of the second gate electrode on the channel layer surface. Optionally, the transistor further includes a first field plate structure, a second field plate structure, a third field plate structure, and a fourth field plate structure; The first field plate structure is positioned between the first electrode and the first gate, the second field plate structure is positioned between the first gate and the second electrode, the third field plate structure is positioned between the second electrode and the second gate, and the fourth field plate structure is positioned between the second gate and the third electrode; The orthographic projection of the first field plate structure on the channel layer surface and the orthographic projection of the second field plate structure on the channel layer surface are symmetrical with respect to the orthographic projection of the first gate on the channel layer surface, and the orthographic projection of the third field plate structure on the channel layer surface and the orthographic projection of the fourth field plate structure on the channel layer surface are symmetrical with respect to the orthographic projection of the second gate on the channel layer surface. Optionally, the first field plate structure is insulated from the first electrode, the second electrode and the third electrode respectively, the second field plate structure is insulated from the first electrode, the second electrode and the third electrode respectively, the third field plate structure is insulated from the first electrode, the second electrode and the third electrode respectively, and the fourth field plate structure is insulated from the first electrode, the second electrode and the third electrode respectively. Optionally, the transistor further includes a fifth field plate structure, a sixth field plate structure, a seventh field plate structure, and an eighth field plate structure; One end of the fifth field plate structure is connected with the second electrode, the other end of the fifth field plate structure is far away from the second electrode along a first direction a, one end of the sixth field plate structure is connected with the second electrode, the other end of the sixth field plate structure is far away from the second electrode along a direction opposite to the first direction a, one end of the seventh field plate structure is connected with the second electrode, the other end of the seventh field plate structure is far away from the second electrode along the first direction a, one end of the eighth field plate structure is connected with the second electrode, the other end of the eighth field plate structure is far away from the second electrode along a direction opposite to the first direction a, and the fifth field plate structure, the sixth field plate structure and the eighth field plate structure are sequentially arranged along a second direction b perpendicular to the first direction a. Optionally, the transistor further comprises a ninth field plate structure and a tenth field plate structure, one end of the