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CN-122002895-A - Transistor and manufacturing method thereof

CN122002895ACN 122002895 ACN122002895 ACN 122002895ACN-122002895-A

Abstract

The present disclosure provides a transistor and a method of fabricating the same. The transistor comprises a channel layer, a barrier layer, a first grid electrode, a second grid electrode, a first electrode, a second electrode and a dielectric layer, wherein the first grid electrode and the second grid electrode comprise a P-type gallium nitride layer, an N-type gallium nitride layer and a grid metal layer, the barrier layer is laminated on the channel layer, the P-type gallium nitride layer and the N-type gallium nitride layer are sequentially laminated on the barrier layer, the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the N-type gallium nitride layer, the first electrode and the second electrode penetrate through the dielectric layer and are in contact with the barrier layer, the grid metal layer penetrates through the dielectric layer and is in contact with the N-type gallium nitride layer, the first electrode, the first grid electrode, the second grid electrode and the first electrode are arranged periodically along a first direction a, the first grid electrode and the second grid electrode are electrically connected, all the first electrodes are electrically connected, and all the second electrodes are electrically connected.

Inventors

  • WANG JUNNAN
  • MO ZHONGYOU
  • CHEN KAI
  • WANG JIANGBO

Assignees

  • 京东方华灿光电(浙江)有限公司

Dates

Publication Date
20260508
Application Date
20251223

Claims (10)

  1. 1. A transistor, characterized in that the transistor comprises a channel layer (101), a barrier layer (102), a gate (34), a first electrode (105), a second electrode (106) and a dielectric layer (107); The grid electrode (34) comprises a P-type gallium nitride layer (201), an N-type gallium nitride layer (202) and a grid metal layer (203); the barrier layer (102) is laminated on the channel layer (101), the P-type gallium nitride layer (201) and the N-type gallium nitride layer (202) are sequentially laminated on the barrier layer (102), the dielectric layer (107) covers the barrier layer (102), the P-type gallium nitride layer (201) and the N-type gallium nitride layer (202), the first electrode (105) and the second electrode (106) penetrate through the dielectric layer (107) and are in contact with the barrier layer (102), and the gate metal layer (203) penetrates through the dielectric layer (107) and is in contact with the N-type gallium nitride layer (202).
  2. 2. A transistor, characterized in that the transistor comprises a channel layer (101), a barrier layer (102), a first gate (103), a second gate (104), a first electrode (105), a second electrode (106) and a dielectric layer (107); The first grid electrode (103) and the second grid electrode (104) comprise a P-type gallium nitride layer (201), an N-type gallium nitride layer (202) and a grid metal layer (203); The barrier layer (102) is laminated on the channel layer (101), the P-type gallium nitride layer (201) and the N-type gallium nitride layer (202) are sequentially laminated on the barrier layer (102), the dielectric layer (107) covers the barrier layer (102), the P-type gallium nitride layer (201) and the N-type gallium nitride layer (202), the first electrode (105) and the second electrode (106) penetrate through the dielectric layer (107) and are in contact with the barrier layer (102), and the gate metal layer (203) penetrates through the dielectric layer (107) and is in contact with the N-type gallium nitride layer (202); Along a first direction a, the first electrode (105), the first grid (103), the second electrode (106), the second grid (104) and the first electrode (105) are arranged periodically, the first grid (103) and the second grid (104) are electrically connected, all the first electrodes (105) are electrically connected with each other, and all the second electrodes (106) are electrically connected with each other.
  3. 3. The transistor according to claim 2, wherein the thickness of the P-type gallium nitride layer (201) is 100-200 nm and the thickness of the N-type gallium nitride layer (202) is 10-50 nm.
  4. 4. The transistor according to claim 2, wherein the doping concentration of Mg in the P-type gallium nitride layer (201) is 1e 18-5 e19cm -3 , and the doping concentration of Si in the N-type gallium nitride layer (202) is 1e 19-3 e19cm -3 .
  5. 5. The transistor according to claim 2, wherein in the first direction a, the distance between the P-type gallium nitride layer (201) and the first electrode (105) or the second electrode (106) is 8-9 μm, and the distance between the N-type gallium nitride layer (202) and the first electrode (105) or the second electrode (106) is 8-9 μm.
  6. 6. The transistor according to claim 5, wherein in the first direction a, the P-type gallium nitride layer (201) and the N-type gallium nitride layer (202) have a width of 1.2-1.8 μm, and the gate metal layer (203) has a width of 0.4-0.6 μm.
  7. 7. The transistor according to any of claims 2 to 6, further comprising a passivation layer (108), a field plate structure (109), a protection layer (110) and a metal interconnect structure (113); The passivation layer (108) is positioned on the dielectric layer (107), the field plate structure (109) passes through the passivation layer (108) to be in contact with the dielectric layer (107), the protection layer (110) covers the field plate structure (109) and the passivation layer (108), the metal interconnection structure (113) passes through the passivation layer (108) to be electrically connected with the first electrode (105) or the second electrode (106), and the protection layer (110) exposes at least part of the surface of the metal interconnection structure (113) through an opening; along the first direction a, the first electrode (105), the field plate structure (109), the first gate (103), the field plate structure (109), the second electrode (106), the field plate structure (109), the second gate (104), the field plate structure (109) and the first electrode (105) are periodically arranged; The field plate structure (109) is electrically connected to the first gate (103) or the second gate (104).
  8. 8. The transistor according to claim 7, characterized in that the width of the field plate structure (109) in the first direction a is 1.2-1.8 μm.
  9. 9. The transistor according to claim 8, wherein in the first direction a, the distance between the field plate structure (109) and the P-type gallium nitride layer (201) or the N-type gallium nitride layer (202) is 0.8-1.2 μm.
  10. 10. A method of fabricating a transistor, the method comprising: Sequentially manufacturing a channel layer and a barrier layer, wherein the barrier layer is laminated on the channel layer; The first grid electrode and the second grid electrode comprise a P-type gallium nitride layer, an N-type gallium nitride layer and a grid metal layer, wherein the P-type gallium nitride layer and the N-type gallium nitride layer are sequentially laminated on the barrier layer; manufacturing a dielectric layer covering the barrier layer, the P-type gallium nitride layer and the N-type gallium nitride layer; And along a first direction a, the first electrode, the first grid electrode, the second grid electrode and the first electrode are arranged periodically, the first grid electrode and the second grid electrode are electrically connected, all the first electrodes are electrically connected with each other, and all the second electrodes are electrically connected with each other.

Description

Transistor and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor devices, and more particularly, to a transistor and a method of fabricating the same. Background GaN-based transistors are candidates for next generation power switching applications due to their excellent device characteristics (low specific on-resistance, low switching loss, and high breakdown voltage). A GaN-based high electron mobility transistor (High Electron Mobility Transistor, HEMT) of polarized superjunction (Polarization Super Junction, PNJ) structure achieves charge balance by alternating P/N type columns. However, the above PNJ structure has a complicated process, high cost, and is difficult to apply in a bidirectional GaN-based HEMT. Disclosure of Invention The embodiment of the disclosure provides a transistor and a manufacturing method thereof, which can simplify a PNJ structure and be applied to a bidirectional GaN-based HEMT. The technical scheme is as follows: In one aspect, a transistor is provided that includes a channel layer, a barrier layer, a gate electrode, a first electrode, a second electrode, and a dielectric layer; The grid electrode comprises a P-type gallium nitride layer, an N-type gallium nitride layer and a grid metal layer; The barrier layer is laminated on the channel layer, the P-type gallium nitride layer and the N-type gallium nitride layer are sequentially laminated on the barrier layer, the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the N-type gallium nitride layer, the first electrode and the second electrode penetrate through the dielectric layer and are in contact with the barrier layer, and the gate metal layer penetrates through the dielectric layer and is in contact with the N-type gallium nitride layer. In another aspect, a transistor is provided that includes a channel layer, a barrier layer, a first gate, a second gate, a first electrode, a second electrode, and a dielectric layer; The first grid electrode and the second grid electrode comprise a P-type gallium nitride layer, an N-type gallium nitride layer and a grid metal layer; The barrier layer is laminated on the channel layer, the P-type gallium nitride layer and the N-type gallium nitride layer are sequentially laminated on the barrier layer, the dielectric layer covers the barrier layer, the P-type gallium nitride layer and the N-type gallium nitride layer, the first electrode and the second electrode penetrate through the dielectric layer to be contacted with the barrier layer, and the gate metal layer penetrates through the dielectric layer to be contacted with the N-type gallium nitride layer; Along a first direction a, the first electrode, the first grid electrode, the second grid electrode and the first electrode are arranged periodically, the first grid electrode and the second grid electrode are electrically connected, all the first electrodes are electrically connected with each other, and all the second electrodes are electrically connected with each other. Optionally, the thickness of the P-type gallium nitride layer is 100-200 nm, and the thickness of the N-type gallium nitride layer is 10-50 nm. Optionally, the doping concentration of Mg in the P-type gallium nitride layer is 1E18-5E19 cm -3, and the doping concentration of Si in the N-type gallium nitride layer is 1E19-3E19 cm -3. Optionally, in the first direction a, a distance between the P-type gallium nitride layer and the first electrode or the second electrode is 8-9 μm, and a distance between the N-type gallium nitride layer and the first electrode or the second electrode is 8-9 μm. Optionally, in the first direction a, the widths of the P-type gallium nitride layer and the N-type gallium nitride layer are 1.2-1.8 μm, and the widths of the gate metal layer are 0.4-0.6 μm. Optionally, the transistor further comprises a passivation layer, a field plate structure, a protection layer and a metal interconnection structure; The passivation layer is positioned on the dielectric layer, the field plate structure is contacted with the dielectric layer through the passivation layer, and the protection layer covers the field plate structure and the passivation layer; the metal interconnection structure is electrically connected with the first electrode or the second electrode through the passivation layer, and the protection layer exposes at least part of the surface of the metal interconnection structure through the opening; The first electrode, the field plate structure, the first gate, the field plate structure, the second electrode, the field plate structure, the second gate, the field plate structure and the first electrode are periodically arranged along the first direction a; the field plate structure is electrically connected with the first grid electrode or the second grid electrode. Optionally, in the first direction a, the width of the field plate structure is 1.2-1.8 μm. Opt