CN-122002898-A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Abstract

A semiconductor device is provided that includes a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate, a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, and a source/drain pattern spaced apart from the gate electrode in a third direction intersecting the first direction and the second direction and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns includes a contact portion at least a portion of which is inserted within the source/drain pattern, and a connection portion extending from the contact portion away from the source/drain pattern in the third direction.

Inventors

• LI SHANGWEN
• JU FENGZHEN
• An Surong
• LIANG XI

Assignees

• 三星电子株式会社

Dates

Publication Date

20260508

Application Date

20250923

Priority Date

20241107

Claims (20)

1. 1. A semiconductor device, the semiconductor device comprising: A plurality of active patterns spaced apart in a first direction intersecting a surface of the substrate; a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, and A source/drain pattern spaced apart from the gate electrode in a third direction intersecting the first direction and the second direction and connected to the plurality of active patterns in the third direction, Wherein each of the plurality of active patterns includes a contact portion at least a portion of which penetrates into the source/drain pattern, and a connection portion extending from the contact portion away from the source/drain pattern in the third direction.
2. 2. The semiconductor device of claim 1, wherein the connection comprises a two-dimensional material.
3. 3. The semiconductor device according to claim 1, wherein the connection portion and the contact portion each comprise a first metal material.
4. 4. The semiconductor device of claim 1, further comprising a gate spacer on a side of the gate electrode in the third direction.
5. 5. The semiconductor device of claim 4, wherein the contact protrudes further toward the source/drain pattern than the gate spacer in the third direction.
6. 6. The semiconductor device of claim 4, wherein at least a portion of the contact overlaps the gate spacer in the first direction.
7. 7. The semiconductor device according to claim 4, wherein a width of the connection portion in the third direction is larger than a width between outer side surfaces of the gate spacers in the third direction.
8. 8. The semiconductor device of claim 4, wherein the gate spacer comprises: an inner spacer located between the plurality of active patterns and the substrate in the first direction, and An outer spacer located on an uppermost active pattern among the plurality of active patterns in the first direction.
9. 9. The semiconductor device of claim 8, wherein a width in the third direction between the outer side surfaces of the outer spacers is greater than a width in the third direction between the outer side surfaces of the inner spacers.
10. 10. The semiconductor device of claim 8, further comprising a protective layer located between the outer spacer and the uppermost active pattern in the first direction.
11. 11. The semiconductor device according to claim 1, wherein a width of the gate electrode is smaller than a width of the connection portion in the third direction.
12. 12. The semiconductor device of claim 2, wherein the contact comprises a transition metal.
13. 13. The semiconductor device of claim 1, wherein an upper surface of the gate electrode and an upper surface of the source/drain pattern are coplanar.
14. 14. A semiconductor device, the semiconductor device comprising: A plurality of active patterns spaced apart in a first direction intersecting a surface of the substrate; A gate structure including a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns and a gate spacer on a side of the gate electrode in a third direction intersecting the first direction and the second direction, and A source/drain pattern spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction, Wherein each of the plurality of active patterns protrudes further toward the source/drain pattern than the gate structure in the third direction, and includes a multi-layered pattern in the third direction.
15. 15. The semiconductor device of claim 14, wherein the multi-layer pattern comprises: A contact portion contacting the source/drain pattern in the third direction, and And a connection portion extending from the contact portion away from the source/drain pattern in the third direction.
16. 16. The semiconductor device of claim 15, wherein the contact comprises a transition metal, and Wherein the connection portion comprises a two-dimensional material including a transition metal.
17. 17. The semiconductor device of claim 15, wherein the contact penetrates into the source/drain pattern.
18. 18. The semiconductor device of claim 14, wherein the gate structure further comprises a gate insulating layer located inside the gate spacer and surrounding the gate electrode in the third direction.
19. 19. The semiconductor device of claim 14, further comprising an interlayer insulating layer between the substrate and the gate structure and the source/drain pattern.
20. 20. A semiconductor device, the semiconductor device comprising: A plurality of active patterns spaced apart in a first direction intersecting a surface of the substrate; A gate structure including a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns and a gate spacer on a side of the gate electrode in a third direction intersecting the first direction and the second direction, and A source/drain pattern spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction, Wherein each of the plurality of active patterns includes a contact portion contacting the source/drain pattern in the third direction, and a connection portion extending away from the source/drain pattern from the contact portion in the third direction, Wherein the contact portion protrudes further toward the source/drain pattern than the gate structure in the third direction, Wherein the connection portion comprises a two-dimensional material, and Wherein the contact portion and the connection portion each include a first transition metal.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Technical Field The present disclosure relates to semiconductor devices. Background As one of scaling techniques for increasing the density of semiconductor devices, a multi-gate transistor in which a silicon body having a fin shape or a nanowire shape is formed on a substrate and a gate electrode is formed on a surface of the silicon body has been proposed. Meanwhile, due to miniaturization of semiconductor devices, resistance problems between elements arise. Disclosure of Invention Embodiments of the present disclosure provide a semiconductor device with reduced resistance. Another embodiment of the present disclosure provides a semiconductor device with improved reliability. The exemplary embodiments are not limited to the above technical features and other technical features not stated may be apparent to those skilled in the art from the following description. According to an embodiment, a semiconductor device is provided that includes a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate, a gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, and a source/drain pattern spaced apart from the gate electrode in a third direction intersecting the first direction and the second direction and connected to the plurality of active patterns in the third direction. Each of the plurality of active patterns may include a contact portion at least a portion of which penetrates into the source/drain pattern, and a connection portion extending from the contact portion away from the source/drain pattern in the third direction. According to another embodiment, a semiconductor device is provided that includes a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate, a gate structure including a gate electrode and a gate spacer extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, the gate spacer being located at a side of the gate electrode in a third direction intersecting the first direction and the second direction, and a source/drain pattern spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction, and each of the plurality of active patterns may protrude further toward the source/drain pattern than the gate structure in the third direction and include a multilayer pattern in the third direction. According to another embodiment, a semiconductor device is provided that includes a plurality of active patterns spaced apart in a first direction intersecting a surface of a substrate, a gate structure including a gate electrode and a gate spacer, the gate electrode extending in a second direction intersecting the first direction and surrounding the plurality of active patterns, the gate spacer being disposed at a side of the gate electrode in a third direction intersecting the first direction and the second direction, and a source/drain pattern spaced apart from the gate structure in the third direction and connected to the plurality of active patterns in the third direction, and each of the plurality of active patterns may include a contact portion that contacts the source/drain pattern in the third direction, and a connection portion that extends away from the contact portion in the third direction from the source/drain pattern, and that may include a further two-dimensional material than the source/drain pattern and may include a transition portion that may protrude in the third direction and may include a further two-dimensional material than the source/drain pattern. Details of example embodiments are included in the detailed description and the accompanying drawings. Drawings These and/or other embodiments, features, and advantages of the present disclosure will become apparent and more readily appreciated from the following description of the exemplary embodiments, taken in conjunction with the accompanying drawings, wherein: fig. 1 is an exemplary diagram showing a schematic layout of a semiconductor device according to some example embodiments; FIG. 2 is an exemplary diagram illustrating a cross section taken along line A-A of FIG. 1; Fig. 3 is an exemplary enlarged view illustrating a portion R of fig. 2; FIG. 4 is an exemplary diagram illustrating a cross section taken along line B-B of FIG. 1; Fig. 5 is an exemplary enlarged view illustrating a portion R of fig. 2 to illustrate a semiconductor device according to other exemplary embodiments; Fig. 6 is an example enlarged view illustrating a portion R of fig. 2 to illustrate a semiconductor device according to some other example embodiments; fig. 7 is an exemplary enlarged view illustrating a portion R of fig. 2 to illustrate a semiconductor device according to other ex