CN-122002900-A - Complementary field effect transistor device structure and preparation method thereof

CN122002900ACN 122002900 ACN122002900 ACN 122002900ACN-122002900-A

Abstract

The invention discloses a complementary field effect transistor device structure and a preparation method thereof, relates to the technical field of transistors, and aims to solve the technical problems that a P-type transistor cannot be realized by a traditional two-dimensional ferroelectric semiconductor material and performance improvement of a traditional silicon-based material is limited under a nanoscale in the prior art. The complementary field effect transistor device structure comprises a substrate, at least one group of heterojunction units formed on the substrate and a double-gate structure arranged corresponding to each group of heterojunction units, wherein the first heterojunction comprises a first two-dimensional ferroelectric semiconductor layer and a first two-dimensional insulating layer, the second heterojunction comprises a second two-dimensional insulating layer and a second two-dimensional ferroelectric semiconductor layer, the second two-dimensional ferroelectric semiconductor layer in the second heterojunction is induced to form P-type semiconductor characteristics by applying external voltage to the double-gate structure, and the first two-dimensional ferroelectric semiconductor layer in the first heterojunction keeps intrinsic N-type semiconductor characteristics, so that the complementary field effect transistor is integrated.

Inventors

XU LIJUN
XU QINZHI
WU ZHENHUA
LUO KUN
LI ZHIQIANG

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260508
Application Date: 20251222

Claims (10)

1. A complementary field effect transistor device structure comprising: A substrate; at least one group of heterojunction units formed on the substrate and a double-gate structure arranged corresponding to each group of heterojunction units; Each group of heterojunction units consists of a first heterojunction and a second heterojunction which are stacked in sequence, wherein the first heterojunction comprises a first two-dimensional ferroelectric semiconductor layer and a first two-dimensional insulating layer which are sequentially arranged from bottom to top; And applying external voltage to the double-grid structure to induce the second two-dimensional ferroelectric semiconductor layer in the second heterojunction to form a P-type semiconductor characteristic, and keeping the intrinsic N-type semiconductor characteristic of the first two-dimensional ferroelectric semiconductor layer in the first heterojunction to realize the integration of a complementary field effect transistor.
2. The complementary field effect transistor device structure of claim 1, wherein the double gate structure comprises a back gate, an intermediate gate layer and a top gate, the back gate and the intermediate gate layer forming a first gate structure, the top gate and the intermediate gate layer forming a second gate structure; The back gate is positioned between the substrate and the first heterojunction, and a first oxide layer is arranged between the back gate and the first heterojunction; the intermediate gate layer is positioned between the first heterojunction and the second heterojunction; the top gate is positioned on one side of the second heterojunction, which is far away from the first heterojunction, and a second oxide layer is arranged between the top gate and the second heterojunction.
3. The complementary field effect transistor device structure of claim 2, wherein a low level is applied to the top gate and the back gate, a high level is applied to the intermediate gate layer, and a polarization direction of the second two-dimensional ferroelectric semiconductor layer in the second heterojunction is away from the second two-dimensional insulating layer.
4. The complementary field effect transistor device structure of claim 3, wherein voltages of the top gate, the back gate and the intermediate gate layer are equal in an operating state after initialization is completed.
5. The complementary field effect transistor device structure of claim 1, wherein the first two-dimensional insulating layer and the second two-dimensional insulating layer are two-dimensional insulating materials having an atomically flat crystalline structure, a uniform chemical bond distribution, and a charge distribution only on an atomic layer surface.
6. The structure of claim 5, wherein in the second heterojunction, the second two-dimensional ferroelectric semiconductor layer is grown in situ on the surface of the second two-dimensional insulating layer away from the substrate in an atomically bonded manner, and the valence band of the second two-dimensional ferroelectric semiconductor layer is induced to be steeper by the charge template effect of the second two-dimensional insulating layer.
7. The complementary field effect transistor device structure of claim 5, wherein the two-dimensional insulating material comprises at least two-dimensional aluminum oxide and boron nitride; The material of the first two-dimensional ferroelectric semiconductor layer and the second two-dimensional ferroelectric semiconductor layer is alpha indium diselenide.
8. The complementary field effect transistor device structure of claim 1, wherein in the first heterojunction, the first two-dimensional ferroelectric semiconductor layer is grown prior to the first two-dimensional insulating layer, and the first two-dimensional insulating layer is formed on a side of the first two-dimensional ferroelectric semiconductor layer away from the substrate by a transfer capping manner.
9. The preparation method of the complementary field effect transistor device structure is characterized by comprising the following steps: Providing a substrate; forming at least one group of heterojunction units and a double-grid structure corresponding to each group of heterojunction units on the substrate; Each group of heterojunction units consists of a first heterojunction and a second heterojunction which are stacked in sequence, wherein the first heterojunction comprises a first two-dimensional ferroelectric semiconductor layer and a first two-dimensional insulating layer which are sequentially arranged from bottom to top; And applying external voltage to the double-grid structure to induce the second two-dimensional ferroelectric semiconductor layer in the second heterojunction to form a P-type semiconductor characteristic, and keeping the intrinsic N-type semiconductor characteristic of the first two-dimensional ferroelectric semiconductor layer in the first heterojunction to realize the integration of a complementary field effect transistor.
10. The method of manufacturing a complementary field effect transistor device structure according to claim 9, wherein forming at least one set of heterojunction cells and a double gate structure disposed in correspondence with each set of heterojunction cells on the substrate comprises: forming a back gate on a substrate; Forming a first oxide layer on the back gate; generating a first two-dimensional ferroelectric semiconductor layer on the first oxide layer; forming a first two-dimensional insulating layer on the first two-dimensional ferroelectric semiconductor layer by a transfer coverage mode; forming a dummy gate sacrificial layer on the first two-dimensional insulating layer; Growing a second two-dimensional insulating layer on the dummy gate sacrificial layer; In-situ growing a second two-dimensional ferroelectric semiconductor layer on the surface of the second two-dimensional insulating layer far away from the substrate in an atomic-scale bonding mode; Growing a protective layer on one side of the second two-dimensional ferroelectric semiconductor layer away from the substrate and etching the protective layer; Depositing metal at the etching position and connecting the through holes; Removing the protective layer and growing a second oxide layer; removing the dummy gate sacrificial layer to form a groove, and depositing a third oxide layer in the groove; and depositing a metal material in the groove area corresponding to the third oxide layer to form an intermediate gate layer.

Description

Complementary field effect transistor device structure and preparation method thereof Technical Field The invention relates to the technical field of transistors, in particular to a complementary field effect transistor device structure and a preparation method thereof. Background CMOS (Complementary Metal-Oxide-Semiconductor) technology is used as a core foundation for modern integrated circuit fabrication, and complex digital logic functions are realized by integrating N-type and P-type MOSFETs (metal Oxide Semiconductor field effect transistors) on the same chip. However, as the semiconductor technology is continuously evolving towards the nanometer scale, the traditional planar transistor and fin field effect transistor (FinFET) gradually approach to the physical limit, so that the problems of short channel effect, increased leakage current and the like are more and more remarkable, further improvement of the chip performance is severely limited, and application requirements of higher integration level, lower power consumption and faster speed are difficult to meet. To continue moore's law, new transistor structures and techniques are needed, CFET (Complementary Field-Effect Transistor, complementary field effect transistor) techniques have evolved. The CFET technology realizes remarkable improvement of transistor density by vertically stacking N-type and P-type transistors, optimizes electrical characteristics, has stronger current driving capability, lower power consumption and leakage current, is especially suitable for scenes sensitive to power consumption, such as mobile equipment, the Internet of things and the like, and marks important transition of transistor structures from two dimensions to three dimensions. The application of the new material is the key of CFET technology development, and the two-dimensional atomic crystal shows excellent short channel control capability in a small-size device by virtue of the structural advantage of atomic layer precision, thereby providing possibility for miniaturization and high performance of CFET. The two-dimensional ferroelectric semiconductor material has the dual advantages of a two-dimensional semiconductor and ferroelectricity, has the thickness of an atomic layer, brings excellent static control capability and immunity to depolarization fields, is superior to the traditional perovskite ferroelectric material, can keep stable ferroelectric polarization at room temperature, can keep the characteristic under the limit of a single layer, can reduce a storage unit to the atomic layer, integrates in the boosting vertical direction to maximize the information storage capacity, and provides an ideal platform for the construction of a memory integrated chip. In theory, the CFET technology based on the two-dimensional ferroelectric semiconductor material can realize the limit scaling of the device size, and combines logic calculation with ferroelectric storage, thereby being an important development direction of the high-efficiency low-power integrated circuit. However, the two-dimensional ferroelectric semiconductor material has inherent defects in the self energy band structure, has small conduction band carrier mass, can only show N-type semiconductor characteristics, has extremely poor P-type characteristics due to the fact that the valence band is close to the flat band, and cannot directly construct a P-type transistor, so that the integration of complementary field effect transistors based on the same two-dimensional ferroelectric semiconductor material system is hindered. Although two-dimensional ferroelectric semiconductor materials have significant advantages in terms of performance, size, functional integration, etc., the prior art has difficulty in using them to manufacture complementary transistors, limiting their application in high-end integrated circuits. Disclosure of Invention The invention aims to provide a complementary field effect transistor device structure and a preparation method thereof, which are used for solving the problem that the complementary field effect transistor device cannot be formed by the same ferroelectric semiconductor material in the prior art. In order to achieve the above object, the present invention provides the following technical solutions: in a first aspect, the present invention provides a complementary field effect transistor device structure comprising: A substrate; at least one group of heterojunction units formed on the substrate and a double-gate structure arranged corresponding to each group of heterojunction units; Each group of heterojunction units consists of a first heterojunction and a second heterojunction which are sequentially stacked, wherein the first heterojunction comprises a first two-dimensional ferroelectric semiconductor layer and a first two-dimensional insulating layer which are sequentially arranged from bottom to top; And applying external voltage to the double-gate structure to ind