CN-122002901-A - Semiconductor device structure and forming method thereof

CN122002901ACN 122002901 ACN122002901 ACN 122002901ACN-122002901-A

Abstract

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region, a contact etch stop layer disposed over the source/drain region, a first inter-layer dielectric (ILD) layer disposed over the contact etch stop layer, an etch stop layer disposed over the contact etch stop layer and the first ILD layer, a second ILD layer disposed over the etch stop layer, a substrate portion disposed under the source/drain region, and an isolation region disposed adjacent to the substrate portion. The isolation region includes a first dielectric layer including a first dielectric material, and a second dielectric layer disposed on the first dielectric layer. The second dielectric layer includes a second dielectric material different from the first dielectric material. The isolation region further includes a hard mask structure disposed on the first dielectric layer and the second dielectric layer.

Inventors

ZHOU JUNYI
CHEN GUANLIN
JIANG GUOCHENG
WANG ZHIHAO

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260508
Application Date: 20251231
Priority Date: 20250507

Claims (10)

1. A semiconductor device structure, comprising: A source/drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, a concentration of the dopant in the first epitaxial layer is different from a concentration of the dopant in the second epitaxial layer, and a thickness of the source/drain region is different from a width of the source/drain region in a cross-sectional view; a contact etch stop layer disposed over the source/drain regions; A first interlayer dielectric layer disposed over the contact etch stop layer; an etch stop layer disposed over a top surface of the contact etch stop layer and a top surface of the first interlayer dielectric layer; a second interlayer dielectric layer disposed over the etch stop layer, wherein a thickness of the first interlayer dielectric layer is greater than a thickness of the second interlayer dielectric layer; A substrate portion disposed under the source/drain region, and An isolation region disposed adjacent to the substrate portion, wherein the isolation region comprises: a first dielectric layer comprising a first dielectric material; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer comprises a second dielectric material different from the first dielectric material, and A hard mask structure is disposed on the first dielectric layer and the second dielectric layer.
2. The semiconductor device structure of claim 1, wherein the hard mask structure comprises an oxide layer and a protective layer disposed on the oxide layer.
3. The semiconductor device structure of claim 2, wherein the protective layer comprises the second dielectric material.
4. The semiconductor device structure of claim 3, wherein the first dielectric material comprises silicon oxide and the second dielectric material comprises SiN, siCN, siOC, siOCN or SiC.
5. The semiconductor device structure of claim 1, further comprising a spacer disposed on the hard mask structure, wherein the spacer is adjacent to the source/drain region.
6. The semiconductor device structure of claim 5, wherein the contact etch stop layer interfaces with the spacer, the hard mask structure, the first dielectric layer, and the second dielectric layer.
7. The semiconductor device structure of claim 1, further comprising a semiconductor layer disposed between the substrate portion and the source/drain regions, wherein the semiconductor layer is adjacent to the hard mask structure.
8. The semiconductor device structure of claim 7, further comprising a third dielectric layer disposed between the semiconductor layer and the source/drain regions.
9. A semiconductor device structure, comprising: A first source/drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, a concentration of the dopant in the first epitaxial layer is different from a concentration of the dopant in the second epitaxial layer, and a thickness of the first source/drain region is different from a width of the first source/drain region in a cross-sectional view; a second source/drain region disposed adjacent to the first source/drain region; a gate electrode layer disposed adjacent to the first source/drain region and the second source/drain region; a contact etch stop layer disposed over the first source/drain region and the second source/drain region; A first interlayer dielectric layer disposed over the contact etch stop layer; an etch stop layer disposed over a top surface of the contact etch stop layer and a top surface of the first interlayer dielectric layer; a second interlayer dielectric layer disposed over the etch stop layer, wherein a thickness of the first interlayer dielectric layer is greater than a thickness of the second interlayer dielectric layer; A first substrate portion disposed under the first source/drain region; a second substrate portion disposed under the second source/drain region, and An isolation region disposed between the first substrate portion and the second substrate portion, wherein the isolation region comprises a first dielectric layer and a hard mask structure disposed over the first dielectric layer, the hard mask structure comprising a first portion and a second portion, wherein the contact etch stop layer extends through the first portion of the hard mask structure and the gate electrode layer is disposed over the second portion of the hard mask structure.
10. A method for forming a semiconductor device structure, comprising: Forming a fin structure over a substrate, wherein the fin structure includes a substrate portion and a first protective layer over the substrate portion; forming an isolation region adjacent the substrate portion, comprising: depositing a first dielectric layer around the fin structure; depositing a second dielectric layer over the first dielectric layer; depositing a third dielectric layer over the second dielectric layer; Recessing the first dielectric layer to expose sides of the first protective layer; removing the first protective layer; recessing the first dielectric layer and the third dielectric layer, and Recessing the first dielectric layer and the second dielectric layer, and A source/drain region is formed over the substrate portion, wherein the source/drain region comprises a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, a concentration of the dopant in the first epitaxial layer is different from a concentration of the dopant in the second epitaxial layer, and a thickness of the source/drain region is different from a width of the source/drain region in a cross-sectional view.

Description

Semiconductor device structure and forming method thereof Technical Field Embodiments of the present application relate to semiconductor device structures and methods of forming the same. Background The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in multi-generation ICs, where each generation has smaller and more complex circuitry than the previous generation. During the development of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such a shrink process generally provides benefits by improving production efficiency and reducing associated costs. Such scaling also increases the complexity of processing and manufacturing ICs. Thus, there is a need for improved processing and manufacturing of ICs. Disclosure of Invention Some embodiments of the present application provide a semiconductor device structure comprising a source/drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, wherein a concentration of the dopant in the first epitaxial layer is different from a concentration of the dopant in the second epitaxial layer, and wherein in a cross-sectional view a thickness of the source/drain region is different from a width of the source/drain region, a contact etch stop layer disposed over the source/drain region, a first interlayer dielectric layer disposed over the contact etch stop layer, an etch stop layer disposed over a top surface of the contact etch stop layer and a top surface of the first interlayer dielectric layer, a second interlayer dielectric layer disposed over the etch stop layer, wherein a thickness of the first interlayer dielectric layer is greater than a thickness of the second interlayer dielectric layer, a substrate portion disposed under the source/drain region, and an isolation region disposed adjacent to the substrate portion, wherein the first interlayer dielectric layer comprises a first dielectric layer and the second dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise a second dielectric layer. Further embodiments of the present application provide a semiconductor device structure comprising a first source/drain region comprising a first epitaxial layer and a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer are doped with a dopant, wherein a concentration of the dopant in the first epitaxial layer is different from a concentration of the dopant in the second epitaxial layer, and wherein in a cross-sectional view a thickness of the first source/drain region is different from a width of the first source/drain region, a second source/drain region disposed adjacent to the first source/drain region, a gate electrode layer disposed adjacent to the first source/drain region and the second source/drain region, a contact etch stop layer disposed over the first source/drain region and the second source/drain region, a first inter-layer dielectric (ILD) layer disposed over the contact etch stop layer, an etch stop layer disposed over a top surface of the contact etch stop layer and a top surface of the first inter-layer dielectric layer, a second inter-layer dielectric layer disposed over a portion of the second dielectric layer, wherein a second dielectric layer is disposed over the first dielectric layer and a portion of the second dielectric layer is disposed over the second dielectric layer, a second dielectric layer is disposed over the first dielectric layer and a portion of the second dielectric layer is disposed over the second dielectric layer, wherein the contact etch stop layer extends through the first portion of the hard mask structure and the gate electrode layer is disposed over the second portion of the hard mask structure. Still further embodiments of the present application provide a method for forming a semiconductor device structure comprising forming a fin structure over a substrate, wherein the fin structure comprises a substrate portion and a first protective layer over the substrate portion, forming an isolation region adjacent to the substrate portion comprising depositing a first dielectric layer around the fin structure, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, recessing the first dielectric layer to expose sides of the first protective layer, removing the first protective layer, recessing the first dielectric layer and the third dielectric layer, and recessing the first dielectric layer and the second dielectric layer, and forming source/drain regions over the substrate portion, wherein the sou