CN-122002902-A - Semiconductor device structure and preparation method thereof

Abstract

The application discloses a semiconductor device structure and a preparation method thereof, and relates to the technical field of semiconductor devices, wherein the semiconductor device structure comprises a substrate, a first transistor, a second transistor and two public side walls, the first transistor is arranged on the substrate, the second transistor is arranged on the first transistor, an isolation layer is arranged between the first transistor and the second transistor, the first transistor comprises a first grid electrode and a first channel region, the first grid electrode is arranged in the first channel region, the second transistor comprises a second grid electrode and a second channel region, and the second grid electrode is arranged in the second channel region; the two public side walls are oppositely arranged on the substrate, and the first channel region and the second channel region are oppositely arranged in the direction perpendicular to the substrate and are positioned between the two public side walls; the application can improve the alignment precision of the first transistor and the second transistor in the direction vertical to the substrate, thereby reducing the preparation difficulty of the stacked semiconductor device structure.

Inventors

• LI YONGJIE

Assignees

• 深圳市鹏新旭技术有限公司

Dates

Publication Date

20260508

Application Date

20260403

Claims (15)

1. 1. A semiconductor device structure, comprising: A substrate; A first transistor and a second transistor, the first transistor is disposed on the substrate, the second transistor is disposed on the first transistor, an isolation layer is disposed between the first transistor and the second transistor, the first transistor comprises a first gate and a first channel region, the first gate is disposed in the first channel region, the second transistor comprises a second gate and a second channel region, the second gate is disposed in the second channel region, and The two public side walls are oppositely arranged on the substrate, and the first channel region and the second channel region are aligned in the direction perpendicular to the substrate and are positioned between the two public side walls.
2. 2. The semiconductor device structure of claim 1, wherein the first transistor further comprises a first source and a first drain, the second transistor further comprises a second source and a second drain; the first source electrode and the second source electrode are aligned in the direction perpendicular to the substrate, the first drain electrode and the second drain electrode are aligned in the direction perpendicular to the substrate, a part of the isolation layer is arranged between the first source electrode and the second source electrode and between the first drain electrode and the second drain electrode, and another part of the isolation layer is arranged between the first channel region and the second channel region The first drain electrode and the second drain electrode are arranged in an alignment mode in the direction perpendicular to the substrate, one part of the isolation layer is arranged between the first source electrode and the second drain electrode and between the first drain electrode and the second source electrode, and the other part of the isolation layer is arranged between the first channel region and the second channel region.
3. 3. The semiconductor device structure of claim 2, wherein the first channel region comprises a plurality of first channel layers, the first channel layer closest to the isolation layer being a first top channel layer disposed between the first gate and the isolation layer, and/or The second channel region comprises a plurality of second channel layers, the second channel layer closest to the isolation layer is a first bottom channel layer, and the first bottom channel layer is arranged between the second grid electrode and the isolation layer.
4. 4. The semiconductor device structure of claim 2, further comprising a plurality of interior sidewalls disposed between the first gate and the first source and the first drain of the first transistor and between the second gate and the second source and the second drain of the second transistor.
5. 5. The semiconductor device structure of claim 2, further comprising a first dielectric layer disposed between the first transistor and the substrate, the first dielectric layer having a plurality of first contact metal layers disposed therein, the first source, first drain, and first gate each being electrically connected to at least one of the first contact metal layers; The second transistor further comprises a second dielectric layer, the second dielectric layer is arranged on one side, far away from the first transistor, of the second transistor, a plurality of second contact metal layers are arranged in the second dielectric layer, and the second source electrode, the second drain electrode and the second grid electrode are respectively and electrically connected with at least one second contact metal layer.
6. 6. A method of manufacturing a semiconductor device structure according to any one of claims 1 to 5, comprising the steps of: Providing a sacrificial substrate, and forming a laminated structure and a virtual grid structure on the sacrificial substrate, wherein the laminated structure comprises a first sub-laminated structure, an isolation sacrificial layer and a second sub-laminated structure; Forming a mask structure, and etching the mask structure and the second sub-laminated structure to form a public side wall and a first groove exposing the isolation sacrificial layer; removing the isolation sacrificial layer and forming an isolation layer, and forming a first transistor on the isolation layer; removing the sacrificial substrate after bonding the substrate on the first transistor and exposing the first sub-stack structure; A second transistor is formed.
7. 7. The method of claim 6, wherein the forming a mask structure and etching the mask structure and the second sub-stack structure to form a common sidewall and expose the first recess of the isolation sacrificial layer comprises: forming a dielectric coating layer on the laminated structure and the virtual grid structure; Forming a first mask layer on the dielectric covering layer, wherein the first mask layer and the dielectric covering layer form the mask structure; And etching the mask structure and the second sub-laminated structure, forming the first grooves exposing the isolation sacrificial layer on two sides of the virtual gate structure, and simultaneously forming the public side walls positioned on the side walls of the virtual gate structure.
8. 8. The method of manufacturing of claim 7, wherein the step of removing the isolation sacrificial layer and forming an isolation layer, forming a first transistor on the isolation layer, comprises: removing the isolation sacrificial layer and forming the isolation layer; etching the end part of the second sub-laminated structure exposed from the side wall of the first groove so as to enable a part of the second sub-laminated structure to be inwards recessed to form a etching-back area; forming an inner side wall in the etching-back region; Forming a first source electrode and a first drain electrode of a first transistor on the isolation layer; And removing a part of the virtual gate structure and a part of the second sub-laminated structure, and forming a first gate of the first transistor.
9. 9. The method of manufacturing of claim 7, wherein the step of removing the isolation sacrificial layer and forming an isolation layer, forming a first transistor on the isolation layer, comprises: etching the end part of the second sub-laminated structure exposed from the side wall of the first groove so as to enable a part of the second sub-laminated structure to be inwards recessed to form a etching-back area; forming an inner side wall in the etching-back region; removing the isolation sacrificial layer and forming the isolation layer; Forming a first source electrode and a first drain electrode of a first transistor on the isolation layer; And removing a part of the virtual gate structure and a part of the second sub-laminated structure, and forming a first gate of the first transistor.
10. 10. The method of manufacturing of claim 9, wherein the step of removing the isolation sacrificial layer and forming the isolation layer comprises: Forming an etching barrier layer; etching the etching barrier layer to expose the isolation sacrificial layer; etching to remove the isolation sacrificial layer; The isolation layer is formed.
11. 11. The method of manufacturing of claim 8 or 9, wherein the step of removing the isolation sacrificial layer and forming the isolation layer is followed by the step of forming a first source and a first drain of the first transistor on the isolation layer, comprising: And removing the first mask layer.
12. 12. The method of manufacturing of claim 6, wherein the step of removing the sacrificial substrate after bonding the substrate on the first transistor and exposing the first sub-stack structure comprises: Bonding a substrate on one side of the first transistor away from the sacrificial substrate to form an intermediate semiconductor structure; the intermediate semiconductor structure is flipped over and the sacrificial substrate is removed to expose the first sub-stack structure.
13. 13. The method of manufacturing of claim 12, wherein the step of removing the sacrificial substrate to expose the first sub-stack structure comprises: Thinning the sacrificial substrate; and etching the thinned sacrificial substrate until the first sub-laminated structure is exposed.
14. 14. The method of manufacturing of claim 12, wherein the step of forming the second transistor comprises: etching the first sub-laminated structure to form second grooves exposing the isolation layer on two sides of the virtual grid structure; forming a second source electrode and a second drain electrode of a second transistor in the second groove; and removing a part of the virtual gate structure and a part of the first sub-laminated structure, and forming a second gate of the second transistor.
15. 15. The method of manufacturing of claim 6, wherein after the step of forming a first transistor on the isolation layer and before the step of bonding a substrate on the first transistor, comprising: Forming a first dielectric layer and a first contact metal layer in the first dielectric layer, and/or After the step of forming the second transistor, comprising: And forming a second dielectric layer and a second contact metal layer positioned in the second dielectric layer.

Description

Semiconductor device structure and preparation method thereof Technical Field The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device structure and a preparation method thereof. Background To further increase the integration level of integrated circuits, a semiconductor device structure in which N-type field effect transistors and P-type field effect transistors are stacked and integrated has been developed. The design can break through the area limitation of the traditional planar complementary metal oxide semiconductor technology, greatly improves the integrated density of the integrated circuit, and has important significance for continuing the Moore's law and reducing the power consumption of the chip. In the prior art, two transistors are stacked vertically, typically by bonding wafers on top of the fabricated lower transistors to prepare the upper transistors. However, this solution has very high requirements for alignment accuracy of the preparation, and thus, difficulty in the preparation process is great. Disclosure of Invention The invention mainly aims to provide a semiconductor device structure and a preparation method thereof, and aims to solve the problem that the preparation of a field effect transistor in the prior art is difficult. To achieve the above object, the present invention provides a semiconductor device structure including: A substrate; A first transistor and a second transistor, the first transistor is disposed on the substrate, the second transistor is disposed on the first transistor, an isolation layer is disposed between the first transistor and the second transistor, the first transistor comprises a first gate and a first channel region, the first gate is disposed in the first channel region, the second transistor comprises a second gate and a second channel region, the second gate is disposed in the second channel region, and The two public side walls are oppositely arranged on the substrate, and the first channel region and the second channel region are aligned in the direction perpendicular to the substrate and are positioned between the two public side walls. In an embodiment, the first transistor further includes a first source and a first drain, and the second transistor further includes a second source and a second drain; the first source electrode and the second source electrode are aligned in the direction perpendicular to the substrate, the first drain electrode and the second drain electrode are aligned in the direction perpendicular to the substrate, a part of the isolation layer is arranged between the first source electrode and the second source electrode and between the first drain electrode and the second drain electrode, and another part of the isolation layer is arranged between the first channel region and the second channel region The first drain electrode and the second drain electrode are arranged in an alignment mode in the direction perpendicular to the substrate, one part of the isolation layer is arranged between the first source electrode and the second drain electrode and between the first drain electrode and the second source electrode, and the other part of the isolation layer is arranged between the first channel region and the second channel region. In one embodiment, the first channel region comprises a plurality of first channel layers, the first channel layer closest to the isolation layer is a first top channel layer disposed between the first gate and the isolation layer, and/or The second channel region comprises a plurality of second channel layers, the second channel layer closest to the isolation layer is a first bottom channel layer, and the first bottom channel layer is arranged between the second grid electrode and the isolation layer. In an embodiment, the semiconductor device structure further includes a plurality of inner sidewalls disposed between the first gate and the first source and the first drain of the first transistor and between the second gate and the second source and the second drain of the second transistor. In an embodiment, the semiconductor device structure further includes a first dielectric layer, the first dielectric layer is disposed between the first transistor and the substrate, a plurality of first contact metal layers are disposed in the first dielectric layer, and the first source electrode, the first drain electrode and the first gate electrode are respectively electrically connected with at least one of the first contact metal layers; The second transistor further comprises a second dielectric layer, the second dielectric layer is arranged on one side, far away from the first transistor, of the second transistor, a plurality of second contact metal layers are arranged in the second dielectric layer, and the second source electrode, the second drain electrode and the second grid electrode are respectively and electrically connected with at least on