CN-122002903-A - Array substrate, preparation method thereof and display panel

CN122002903ACN 122002903 ACN122002903 ACN 122002903ACN-122002903-A

Abstract

The array substrate comprises a substrate, a first conductive layer, an active layer, a grid layer and a source-drain electrode layer, wherein the grid layer comprises a first conductive pattern, the source-drain electrode layer comprises a first electrode wire and a second electrode wire, the first electrode wire comprises a plurality of first electrodes, the second electrode wire comprises a plurality of second electrodes which are arranged separately, the first electrodes and the second electrodes are located in a spacing area, the first conductive layer comprises first wirings, the end parts of the second electrodes are connected with the first wirings through second through holes, the first conductive pattern comprises first extending sections adjacent to the first wirings, the orthographic projection of the first extending sections and the first wirings does not overlap or the orthographic projection of the first extending sections and the first wirings does not overlap, the first conductive layer further comprises a first metal part which is arranged separately from the first wirings, and the orthographic projection of the first metal part and the conductive patterns other than the first extending sections in the first conductive patterns has a second overlapping area.

Inventors

WANG JUN
CHENG JUN
WANG HAITAO
FANG JINGANG

Assignees

合肥鑫晟光电科技有限公司
京东方科技集团股份有限公司
北京京东方技术开发有限公司

Dates

Publication Date: 20260508
Application Date: 20260209

Claims (11)

1. The array substrate is characterized by comprising a substrate and a first conductive layer, an active layer, a gate layer and a source-drain electrode layer which are sequentially distributed on one side of the substrate; the active layer includes an active portion extending in a first direction; The grid layer comprises a first conductive pattern, the first conductive pattern is a continuous extension pattern, the orthographic projection of the first conductive pattern and the active part on the substrate base plate is provided with a plurality of first overlapping areas which are distributed at intervals in a first direction, and a spacing area is formed between two adjacent first overlapping areas; The source electrode layer comprises a second conductive pattern, the second conductive pattern is not overlapped with the orthographic projection of the first conductive pattern on the substrate, the second conductive pattern comprises a first electrode wire and a second electrode wire, the first electrode wire is a continuous extending pattern, the first electrode wire comprises a plurality of first electrodes, the second electrode wire comprises a plurality of second electrodes which are arranged separately, the orthographic projections of the first electrodes and the second electrodes on the substrate are positioned in the interval area, the first electrodes and the second electrodes are sequentially and alternately distributed in a first direction, one first overlapping area is distributed between the adjacent first electrodes and second electrodes, and the first electrodes and the second electrodes are connected to the active part through first through holes; The first conductive layer comprises first wires, the end parts of the second electrodes are connected with the first wires through second through holes, and the first conductive patterns comprise first extension sections which extend along the first direction and are adjacent to the first wires; Wherein, the The first extension section is not overlapped with the orthographic projection of the first wiring on the substrate base plate, or The first extending section overlaps with the orthographic projection of the first wire on the substrate, the first conductive layer further comprises a first metal part which is separately arranged with the first wire, and the orthographic projection of the first metal part adjacent to the first extending section and outside the first extending section in the first conductive pattern on the substrate has a second overlapping area.
2. The array substrate of claim 1, wherein the first extension segment does not overlap with an orthographic projection of the first trace on the substrate; The first conductive pattern further comprises a second extending section and a plurality of grid portions, the second extending section extends along a first direction, the grid portions extend along a second direction and are distributed at intervals along the first direction, the grid portions and orthographic projection of the active portions on the substrate form a first overlapping area, the first extending section, the second extending section and the grid portions define first openings and second openings which are distributed alternately in sequence along the first direction, the directions of the first openings and the second openings are opposite, the first electrode is at least partially located in the first openings, the second electrode is at least partially located in the second openings, and the second direction intersects with the first direction.
3. The array substrate of claim 2, wherein the first electrode line further comprises a connection line extending in a first direction, an end of the first electrode extends from the first opening to connect with the connection line, and an end of the second electrode extends from the second opening to connect with the first trace through the second via.
4. The array substrate of claim 1, wherein the first extension segment overlaps with an orthographic projection of the first trace on a substrate; The first conductive pattern further comprises a second extension section and a plurality of grid electrode parts, the second extension section extends along a first direction, the grid electrode parts extend along a second direction and are distributed at intervals along the first direction, orthographic projections of the grid electrode parts and the active parts on the substrate base plate form a first overlapping area, the first extension section, the second extension section and the grid electrode parts define a third opening and a closed area which are distributed alternately in sequence along the first direction, the first electrode is at least partially arranged in the third opening, the second electrode is arranged in the closed area, the first conductive layer further comprises a second metal part connected with the first wiring, orthographic projections of the second metal part and the end parts of the second electrode on the substrate base plate are provided with a third overlapping area, the second via hole is located in the third overlapping area, and the second direction intersects with the first direction.
5. The array substrate according to any one of claims 1 to 4, wherein a length of the first metal portion in the first direction is greater than a length of the gate portion in the first direction, and an orthographic projection of the first metal portion on the substrate covers an orthographic projection of the gate portion on the substrate at a corresponding position.
6. The array substrate according to any one of claims 1 to 4, wherein the active layer includes a plurality of active portions, the plurality of active portions are located on the same side of the first trace and are distributed at intervals along the second direction, the orthographic projection of the first conductive pattern and any one of the active portions on the substrate has a plurality of first overlapping regions distributed at intervals along the first direction, and positions of the first overlapping regions corresponding to different active portions in the first direction are the same.
7. The array substrate of claim 6, wherein the first conductive layer includes two first traces disposed side by side along a second direction, the active layer includes two active portion groups, any one of the active portion groups includes a plurality of active portions, the gate layer includes two first conductive patterns, the source drain electrode layer includes two second conductive patterns, the two first conductive patterns, the two second conductive patterns, and the two active portion groups are symmetrically disposed on opposite sides of a first center line, the first center line is a middle line of the two first traces, and the active portion groups, the first conductive patterns, the second conductive patterns, and the first traces located on the same side of the first center line form a parallel structure of thin film transistors.
8. The array substrate of claim 1, wherein an insulating layer is disposed between any adjacent film layers of the first conductive layer, the active layer, the gate layer, and the source-drain electrode layer, and/or The material of the active layer is an oxide semiconductor material.
9. The array substrate of claim 1, wherein the substrate comprises a display region and a non-display region, and the first trace, the active portion, the first conductive pattern, and the second conductive pattern are all disposed in the non-display region.
10. A display panel comprising an array substrate according to any one of claims 1 to 9.
11. The preparation method of the array substrate is characterized by comprising the following steps of: Providing a substrate; Sequentially forming a first conductive layer, a buffer layer, an active layer, a gate insulating layer, a gate layer and an interlayer dielectric layer on one side of the substrate, wherein the first conductive layer comprises a first wiring, the active layer comprises an active part extending along a first direction, the gate layer comprises a first conductive pattern, the first conductive pattern is a continuous extending pattern, orthographic projection of the first conductive pattern and the active part on the substrate is provided with a plurality of first overlapping areas distributed at intervals in the first direction, a spacing area is formed between two adjacent first overlapping areas, and the first conductive pattern comprises a first extending section extending along the first direction and adjacent to the first wiring; Forming a first via hole penetrating through the interlayer dielectric layer and the gate insulating layer through a first opening process, wherein the first via hole is positioned in orthographic projection of the spacing region and the first wiring on the substrate; Penetrating the first via hole at the first wiring position to the first conductive layer through a second opening process to form a second via hole; Forming a source-drain electrode layer on one side of the interlayer dielectric layer far away from the substrate, wherein the source-drain electrode layer comprises a second conductive pattern, the second conductive pattern is not overlapped with the orthographic projection of the first conductive pattern on the substrate, the second conductive pattern comprises a first electrode wire and a second electrode wire, the first electrode wire is a continuous extending pattern, the first electrode wire comprises a plurality of first electrodes, the second electrode wire comprises a plurality of second electrodes which are arranged separately, the orthographic projections of the first electrodes and the second electrodes on the substrate are positioned in the interval area, the first electrodes and the second electrodes are alternately distributed in sequence in a first direction, one first overlapping area is distributed between the adjacent first electrodes and second electrodes, the first electrodes and the second electrodes are connected to the active part through the first through holes, and the end parts of the second electrodes are connected with the first wiring through the second through holes; Wherein, the The first extension section is not overlapped with the orthographic projection of the first wiring on the substrate base plate, or The first extending section overlaps with the orthographic projection of the first wire on the substrate, the first conductive layer further comprises a first metal part which is separately arranged with the first wire, and the orthographic projection of the first metal part adjacent to the first extending section and outside the first extending section in the first conductive pattern on the substrate has a second overlapping area.

Description

Array substrate, preparation method thereof and display panel Technical Field The present disclosure relates to the field of display technology. More particularly, to an array substrate, a preparation method thereof and a display panel. Background In Organic LIGHT EMITTING Diode (OLED) display products, the GOA region is often designed with a long channel TFT (Thin Film Transistor ), but the GATE (GATE) and Source Drain (SD) traces are prone to electrostatic failure in the overlapping region. In order to solve the problem of poor static electricity, the conventional scheme uses a jumper wire mode to connect source and drain wires of the GOA region through other layers of metal wires. However, in practical products, this approach can lead to new sites of high static electricity generation, affecting the thin film transistor electrical performance. Disclosure of Invention The disclosure aims to provide an array substrate, a preparation method thereof and a display panel, so as to solve at least one of the technical problems. In order to achieve the above purpose, the present disclosure adopts the following technical scheme: the first aspect of the present disclosure provides an array substrate, including a substrate, and a first conductive layer, an active layer, a gate layer, and a source-drain electrode layer sequentially distributed on one side of the substrate; the active layer includes an active portion extending in a first direction; The grid layer comprises a first conductive pattern, the first conductive pattern is a continuous extension pattern, the orthographic projection of the first conductive pattern and the active part on the substrate base plate is provided with a plurality of first overlapping areas which are distributed at intervals in a first direction, and a spacing area is formed between two adjacent first overlapping areas; The source electrode layer comprises a second conductive pattern, the second conductive pattern is not overlapped with the orthographic projection of the first conductive pattern on the substrate, the second conductive pattern comprises a first electrode wire and a second electrode wire, the first electrode wire is a continuous extending pattern, the first electrode wire comprises a plurality of first electrodes, the second electrode wire comprises a plurality of second electrodes which are arranged separately, the orthographic projections of the first electrodes and the second electrodes on the substrate are positioned in the interval area, the first electrodes and the second electrodes are sequentially and alternately distributed in a first direction, one first overlapping area is distributed between the adjacent first electrodes and second electrodes, and the first electrodes and the second electrodes are connected to the active part through first through holes; The first conductive layer comprises first wires, the end parts of the second electrodes are connected with the first wires through second through holes, and the first conductive patterns comprise first extension sections which extend along the first direction and are adjacent to the first wires; Wherein, the The first extension section is not overlapped with the orthographic projection of the first wiring on the substrate base plate, or The first extending section overlaps with the orthographic projection of the first wire on the substrate, the first conductive layer further comprises a first metal part which is separately arranged with the first wire, and the orthographic projection of the first metal part adjacent to the first extending section and outside the first extending section in the first conductive pattern on the substrate has a second overlapping area. Optionally, the orthographic projection of the first extension section and the first trace on the substrate is not overlapped; The first conductive pattern further comprises a second extending section and a plurality of grid portions, the second extending section extends along a first direction, the grid portions extend along a second direction and are distributed at intervals along the first direction, the grid portions and orthographic projection of the active portions on the substrate form a first overlapping area, the first extending section, the second extending section and the grid portions define first openings and second openings which are distributed alternately in sequence along the first direction, the directions of the first openings and the second openings are opposite, the first electrode is at least partially located in the first openings, the second electrode is at least partially located in the second openings, and the second direction intersects with the first direction. Optionally, the first electrode wire further includes a connection line extending along a first direction, an end portion of the first electrode extends from the first opening to be connected with the connection line, and an end portion of the second electrode ex