CN-122002906-A - Electrostatic discharge device and method of operating the same

Abstract

According to some embodiments, a device includes a reference power supply pad, a negative power supply pad, a resistor connected to the negative power supply pad, and a first transistor connected to the reference power supply pad and the negative power supply pad and having a first gate electrode connected to the resistor, wherein the first transistor is operable to shunt current to the negative power supply pad in response to an electrostatic voltage being applied to one of the reference power supply pad or the negative power supply pad.

Inventors

• YI YAN
• M.Qian

Assignees

• 英飞凌科技有限责任公司

Dates

Publication Date

20260508

Application Date

20251103

Priority Date

20241105

Claims (20)

1. 1. A device, comprising: A reference power supply pad; A negative supply pad; A resistor connected to the negative power supply pad, and A first transistor connected to the reference power supply pad and the negative power supply pad and having a first gate electrode connected to the resistor, wherein the first transistor is operable to shunt current to the negative power supply pad in response to an electrostatic voltage being applied to one of the reference power supply pad or the negative power supply pad.
2. 2. The device of claim 1, comprising: a second transistor connected to at least one of the reference power supply pad or the negative power supply pad in series with the first transistor and having a second gate electrode connected to the resistor.
3. 3. The device of claim 1, wherein: The first transistor includes an n-type transistor.
4. 4. The device of claim 1, comprising: a diode connected between the reference power supply pad and the negative power supply pad, wherein an anode of the diode is connected to the negative power supply pad.
5. 5. The device of claim 1, comprising: positive power supply pad, and And the power supply clamping circuit is connected between the positive power supply pad and the reference power supply pad.
6. 6. The device of claim 5, comprising: A first diode connected between the reference power supply pad and the negative power supply pad, and A second diode connected between the reference power supply pad and the positive power supply pad.
7. 7. A device, comprising: A substrate; a metallization structure located over the substrate, the metallization structure comprising: reference power supply pad, and A negative supply pad; A first well having a first conductivity type, the first well being located in the substrate; a second well having a second conductivity type, the second well being located in the first well; a first contact having the first conductivity type, the first contact being located in the second well and connected to the reference power supply pad; A second contact having the first conductivity type, the second contact being located in the second well and connected to the negative supply pad; a first gate electrode located between the first contact and the second contact, and A resistor connected between the first gate electrode and the negative supply pad.
8. 8. The device of claim 7, comprising: A third contact portion having the first conductivity type in the second well, and A second gate electrode located between the second contact and the third contact, wherein: The resistor is connected between the second gate electrode and the negative supply pad.
9. 9. The device of claim 7, comprising: a third contact having the second conductivity type in the second well and connected to the negative supply pad.
10. 10. The device of claim 7, comprising: A third contact having the first conductivity type in the first well and connected to the reference power supply pad.
11. 11. The device of claim 7, comprising: a silicide blocking layer over portions of the first contact, the second contact, and the first gate electrode.
12. 12. The device of claim 7, wherein: The first conductivity type includes n-type conductivity, and The second conductivity type comprises p-type conductivity.
13. 13. The device of claim 7, comprising: a third well having the first conductivity type in the substrate; a third contact portion having the first conductivity type in the third well and connected to the reference power supply pad, and A fourth contact having the second conductivity type in the third well and connected to the negative supply pad.
14. 14. The device of claim 7, wherein: the metallization structure includes a positive power pad, and The device further comprises: a third well having the first conductivity type in the substrate; a third contact portion having the first conductivity type in the third well and connected to the reference power supply pad, and A fourth contact having the second conductivity type in the third well and connected to the positive power supply pad.
15. 15. A method, comprising: connecting the resistor to a negative power pad; connecting a first transistor between a reference power supply pad and the negative supply pad; connecting the resistor to a first gate electrode of the first transistor, and Current is shunted to the negative supply pad through the first transistor in response to an electrostatic voltage being applied to the reference supply pad.
16. 16. The method of claim 15, comprising: Connecting a second transistor between the reference power supply pad and the negative power supply pad in series with the first transistor; connecting the resistor to a second gate electrode of the second transistor, and The current is shunted to the negative supply pad through the first transistor and the second transistor in response to the electrostatic voltage being applied to the reference supply pad.
17. 17. The method of claim 15, comprising: Connecting a diode between the reference power supply pad and the negative power supply pad, wherein an anode of the diode is connected to the negative power supply pad, and In response to a second electrostatic voltage being applied to the negative supply pad: shunting a second current through the first transistor to the reference supply pad, and A third current is shunted to the reference supply pad through the diode.
18. 18. The method of claim 15, comprising: connecting a power supply clamp circuit between a positive power supply pad and the reference power supply pad, and A second current is shunted to the negative supply pad through the supply clamp circuit and the first transistor in response to a second electrostatic voltage being applied to the positive supply pad.
19. 19. The method of claim 18, comprising: Connecting a first diode between the reference power supply pad and the negative power supply pad, wherein an anode of the first diode is connected to the negative power supply pad; Connecting a second diode between the reference power supply pad and the positive power supply pad, wherein an anode of the second diode is connected to the reference power supply pad, and In response to a third electrostatic voltage being applied to the negative supply pad: shunting a third current to the positive power supply pad through the first transistor and the power supply clamp circuit, and A fourth current is shunted to the positive power supply pad through the first diode and the second diode.
20. 20. The method according to claim 15, wherein: connecting the first transistor to the reference power supply pad and the negative power supply pad includes: an n-type transistor is connected to the reference power supply pad and the negative power supply pad.

Description

Electrostatic discharge device and method of operating the same Technical Field The present disclosure relates generally to electronic circuits, and more particularly, to electrostatic discharge (ESD) protection circuits for negative supply pads. Background An Integrated Circuit (IC) device may include ESD protection circuitry designed to protect the IC from transient events such as ESD events and surges. ESD protection circuits are typically designed to conduct and form a current discharge path to shunt large ESD currents and clamp the voltage of input/output (I/O) pads and power supply pads to a sufficiently low level to prevent IC damage during an ESD event. ESD protection circuits typically facilitate low resistance paths to inhibit voltage build-up to a level that may cause damage. Disclosure of Invention This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key factors or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. According to some embodiments, a device includes a reference power supply pad, a negative power supply pad, a resistor connected to the negative power supply pad, and a first transistor connected to the reference power supply pad and the negative power supply pad and having a first gate electrode connected to the resistor, wherein the first transistor is operable to shunt current to the negative power supply pad in response to an electrostatic voltage being applied to one of the reference power supply pad or the negative power supply pad. According to some embodiments, a device includes a substrate, a metallization structure over the substrate, the metallization structure including a reference power supply pad and a negative power supply pad, a first well having a first conductivity type in the substrate, a second well having a second conductivity type in the first well, a first contact having the first conductivity type in the second well and connected to the reference power supply pad, a second contact having the first conductivity type in the second well and connected to the negative power supply pad, a first gate electrode between the first contact and the second contact, and a resistor connected between the first gate electrode and the negative power supply pad. According to some embodiments, a method includes connecting a resistor to a negative supply pad, connecting a first transistor between a reference supply pad and the negative supply pad, connecting the resistor to a first gate electrode of the first transistor, and shunting current through the first transistor to the negative supply pad in response to an electrostatic voltage being applied to the reference supply pad. According to some embodiments, a system includes means for connecting a resistor to a negative supply pad, means for connecting a first transistor between a reference supply pad and the negative supply pad, means for connecting the resistor to a first gate electrode of the first transistor, and means for shunting current through the first transistor to the negative supply pad in response to an electrostatic voltage being applied to the reference supply pad. To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth certain illustrative aspects and implementations. These are indicative of but a few of the various ways in which one or more aspects may be employed. Other aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in conjunction with the drawings. Drawings Fig. 1A is a schematic diagram of an integrated circuit device having an electrostatic discharge protection circuit connected to a negative supply pad, in accordance with some embodiments. Fig. 1B and 1C are diagrams illustrating the operation of an electrostatic discharge protection circuit according to some embodiments. Fig. 2 is a cross-sectional view of an electrostatic discharge protection circuit in accordance with some embodiments. Fig. 3 is a layout diagram of an electrostatic discharge protection circuit in accordance with some embodiments. Fig. 4 is a flow chart of a method for providing electrostatic discharge protection according to some embodiments. Detailed Description The claimed subject matter is now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. It may be evident, however, that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order t