CN-122002922-A - Image sensor pixel cell with multiple gate transfer transistors

Abstract

The present disclosure relates to an image sensor pixel cell having multiple gate transfer transistors. A pixel cell for an image sensor includes a first photodiode, a second photodiode, and a floating diffusion each disposed within a semiconductor material. The pixel cell further includes a multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion in order to transfer image charge from either the first photodiode or the second photodiode to the floating diffusion. The multiple gate transfer transistor includes a plurality of spaced apart gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion. The multiple gate transfer transistor further includes an isolation structure disposed within the semiconductor substrate between the first photodiode and the second photodiode.

Inventors

• MAO DULI
• LIU YUANLIANG
• Bill pan
• CUI YUNYI
• QIU BAIJUN
• T. Goitz

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260508

Application Date

20250516

Priority Date

20241107

Claims (20)

1. 1. A pixel cell for an image sensor, comprising: a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material, and A multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion so as to transfer image charge from the first photodiode or the second photodiode to the floating diffusion, wherein the multi-gate transfer transistor includes: a plurality of spaced apart gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion, and An isolation structure disposed within the semiconductor material between the first photodiode and the second photodiode.
2. 2. The pixel cell of claim 1, wherein the isolation structure is further disposed between the first gate electrode and the second gate electrode when the pixel cell is viewed from a plan view.
3. 3. The pixel cell of claim 2, wherein the multi-gate transfer transistor further comprises a gate dielectric disposed between the semiconductor material and each of the first gate electrode, the second gate electrode, and the shared gate electrode, wherein the isolation structure includes a trench isolation structure and an isolation implant region aligned with the trench isolation structure, wherein the isolation implant region is oppositely doped relative to the first photodiode and the second photodiode, and wherein the isolation implant region is disposed between the trench isolation structure and the gate dielectric.
4. 4. The pixel cell of claim 1, wherein the multi-gate transfer transistor further comprises: A gate dielectric disposed between the semiconductor material and each of the first gate electrode, the second gate electrode, and the shared gate electrode, and A doped channel region disposed within the semiconductor material proximate the shared gate electrode, wherein the doped channel region extends from the floating diffusion toward the first photodiode or the second photodiode, wherein the doped channel region is spaced apart from the first photodiode and the second photodiode, and wherein the doped channel region is of the same conductivity type relative to the floating diffusion.
5. 5. The pixel cell of claim 1, wherein the first gate electrode, the second gate electrode, and the shared gate electrode extend along a common lateral plane parallel to a first side of the semiconductor material.
6. 6. The pixel cell of claim 1, wherein the shared gate electrode is disposed between the floating diffusion and the first gate electrode when the pixel cell is viewed from a plan view, wherein the shared gate electrode is further disposed between the floating diffusion and the second gate electrode when the pixel cell is viewed from the plan view.
7. 7. The pixel cell of claim 1, further comprising: a third photodiode and a fourth photodiode, each disposed within the semiconductor material, and A second multi-gate transfer transistor configured to selectively couple the third photodiode and the fourth photodiode to the floating diffusion so as to transfer image charge from the third photodiode or the fourth photodiode to the floating diffusion, wherein the second multi-gate transfer transistor includes: A plurality of second spaced apart gate electrodes including a third gate electrode disposed proximate to the third photodiode, a fourth gate electrode disposed proximate to the fourth photodiode, and a second shared gate electrode disposed proximate to the floating diffusion.
8. 8. The pixel cell of claim 7, wherein the floating diffusion is disposed between the shared gate electrode and the second shared gate electrode when the pixel cell is viewed from a plan view, wherein the shared gate electrode and the second shared gate electrode are each disposed between the first gate electrode and the third gate electrode, and wherein the shared gate electrode and the second shared gate electrode are each further disposed between the second gate electrode and the fourth gate electrode.
9. 9. The pixel cell of claim 1, wherein a first longitudinal edge of the first gate electrode is parallel to a second longitudinal edge of the second gate electrode, and wherein a third longitudinal edge of the shared gate electrode is perpendicular to the first longitudinal edge of the first gate electrode and the second longitudinal edge of the second gate electrode, wherein a fourth longitudinal edge of the shared gate electrode is parallel to the third longitudinal edge, and wherein the fourth longitudinal edge is less than the third longitudinal edge.
10. 10. The pixel cell of claim 1, wherein the first and second gate electrodes at least partially enclose the shared gate electrode such that the shared gate electrode is separated from the first and second photodiodes by the first and second gate electrodes, respectively.
11. 11. The pixel cell of claim 1, further comprising circuitry formed within a transistor region, wherein the floating diffusion is disposed between the shared gate electrode and the circuitry.
12. 12. An image sensor, comprising: a pixel unit included in a plurality of pixel units arranged in rows and columns to form a pixel unit array, wherein the pixel unit includes: a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material, and A multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion so as to transfer image charge from the first photodiode or the second photodiode to the floating diffusion, wherein the multi-gate transfer transistor includes: a plurality of spaced apart gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion, and A control circuit configured to control operation of the image sensor.
13. 13. The image sensor of claim 12, wherein the control circuit is further configured to initiate a first charge transfer period of the first photodiode by simultaneously applying a first voltage to the first gate electrode and a second voltage to the shared gate electrode.
14. 14. The image sensor of claim 13, wherein the first voltage and the second voltage are each positive, and wherein during the first charge transfer period, the second voltage applied to the shared gate electrode is greater than the first voltage applied to the first gate electrode to form a potential gradient to facilitate transfer of image charge from the first photodiode to the floating diffusion.
15. 15. The image sensor of claim 13, wherein the control circuit is further configured to terminate the first charge transfer period of the first photodiode by converting the first voltage applied to the first gate electrode to a third voltage and further converting the second voltage applied to the shared gate electrode to a fourth voltage.
16. 16. The image sensor of claim 15, wherein the third voltage is negative and the fourth voltage is negative or zero, and wherein the fourth voltage is greater than the third voltage.
17. 17. The image sensor of claim 15, wherein the control circuit is further configured such that the converting the second voltage applied to the shared gate electrode to the fourth voltage occurs after the converting the first voltage applied to the first gate electrode to the third voltage.
18. 18. The image sensor of claim 12, wherein voltage levels applied to the first gate electrode, the second gate electrode, and the shared gate electrode configured by the control circuit correspond to low level voltages during a high conversion gain readout operation of the pixel cell.
19. 19. The image sensor of claim 12, wherein during a low conversion gain readout operation of the pixel cell, a voltage level applied to the first gate electrode and the second gate electrode configured by the control circuit corresponds to a low level voltage, and a voltage level applied to the shared gate electrode corresponds to a high level voltage, and wherein the high level voltage is greater than the low level voltage.
20. 20. The image sensor of claim 12, wherein the shared gate electrode of the multi-gate transfer transistor is configured to be biased to different voltage levels to modulate a conversion gain of the pixel cell during readout, wherein a separation between the shared gate electrode and both the first gate electrode and the second gate electrode provides isolation between the floating diffusion and both the first photodiode and the second photodiode.

Description

Image sensor pixel cell with multiple gate transfer transistors Technical Field The present disclosure relates generally to image sensors, and in particular, but not exclusively, to CMOS image sensors and applications thereof. Background Image sensors are one type of semiconductor device that has become ubiquitous and is now widely used in digital cameras, cellular telephones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, etc. (e.g., resolution, power consumption, dynamic range, size, etc.) in as much as possible through both device architecture design and image acquisition processing. However, it should be appreciated that many of these metrics are inversely related. For example, pixel size may be increased to improve dynamic range, but this may result in increased noise. In another example, the resolution may be increased by increasing the number of pixels, but if the pixel size is maintained unchanged, the physical size of the image sensor may increase. Accordingly, it remains challenging to improve one or more performance metrics of a semiconductor device, such as an image sensor, while mitigating adverse effects on other performance metrics. Typical image sensors operate in response to image light reflected from an external scene being incident on the image sensor. An image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of incident image light and generate image charge upon absorption of the image light. The image charge generated by the pixel light can be measured as an analog output image signal on the column bit line as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of image light that is read out from the column bit lines as an analog image signal and converted to digital values to generate a digital image (i.e., image data) representing an external scene. Disclosure of Invention An embodiment of the present disclosure provides a pixel cell for an image sensor comprising a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material, and a multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion so as to transfer image charge from the first photodiode or the second photodiode to the floating diffusion, wherein the multi-gate transfer transistor includes a plurality of spaced apart gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion, and an isolation structure disposed within the semiconductor material between the first photodiode and the second photodiode. Another embodiment of the present disclosure provides an image sensor comprising a pixel cell included in a plurality of pixel cells arranged in rows and columns to form an array of pixel cells, wherein the pixel cells include a first photodiode, a second photodiode, and a floating diffusion, each disposed within a semiconductor material, and a multi-gate transfer transistor configured to selectively couple the first photodiode and the second photodiode to the floating diffusion so as to transfer image charge from the first photodiode or the second photodiode to the floating diffusion, wherein the multi-gate transfer transistor includes a plurality of spaced apart gate electrodes including a first gate electrode disposed proximate to the first photodiode, a second gate electrode disposed proximate to the second photodiode, and a shared gate electrode disposed proximate to the floating diffusion, and a control circuit configured to control operation of the image sensor. Drawings Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all examples of elements are necessarily labeled in order not to clutter the drawings where appropriate. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles described. Fig. 1A illustrates a plan view of a pixel cell included in an image sensor having a multi-gate transfer transistor according to an embodiment of the present disclosure. Fig. 1B illustrates a cross-sectional view along line W-W' of the pixel cell in fig. 1A, according to an embodiment of the disclosure. Fig. 1C illustrates a cross-sectional view along line Y-Y' of the pixel cell in fig. 1A, according to an embodiment of the disclosure. Fig. 1D illustrates a schematic diagram of readout of the pixel cell in fig. 1A,