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CN-122002924-A - Chip package and method for manufacturing the same

CN122002924ACN 122002924 ACN122002924 ACN 122002924ACN-122002924-A

Abstract

The present invention relates to a chip package and a method for manufacturing the same, the chip package comprises a semiconductor substrate, bonding adhesive, a support member, a first protection layer and a second protection layer. The top surface of the semiconductor substrate is provided with a conductive pad and a sensing area, and the corners of the top surface of the semiconductor substrate are provided with grooves. The bonding glue is located in the groove. The support piece covers the bonding adhesive and the conductive pad and surrounds the sensing area. The first protection layer is positioned on the bottom surface of the semiconductor substrate. The second protective layer covers the first protective layer, the side wall of the semiconductor substrate and the side face of the bonding adhesive. The grooves and the bonding adhesive therein can prevent stress from being transmitted to the inside of the semiconductor substrate and damage. In addition, the second protection layer can effectively prevent moisture from entering the chip package body and prevent noise light from entering from the side face of the semiconductor substrate.

Inventors

  • HUANG YUTING
  • SUN WEILUN
  • CHEN BAIRONG

Assignees

  • 精材科技股份有限公司

Dates

Publication Date
20260508
Application Date
20251031
Priority Date
20251016

Claims (20)

  1. 1. A chip package, comprising: the semiconductor substrate, its top surface has conductive pad and sensing area, and the corner of the top surface has grooves; bonding glue located in the groove; the support piece covers the bonding adhesive and the conductive pad and surrounds the sensing area; A first protective layer on the bottom surface of the semiconductor substrate, and And the second protective layer covers the first protective layer, the side wall of the semiconductor substrate and the side face of the bonding adhesive.
  2. 2. The chip package of claim 1, wherein corners of the bottom surface of the support have notches, and the second passivation layer extends into the notches.
  3. 3. The die package as recited in claim 1, further comprising: And the light-transmitting sheet is positioned on the supporting piece and above the sensing area.
  4. 4. The wafer package of claim 3, wherein the second protective layer further covers sidewalls of the support, sidewalls of the light transmissive sheet and a top surface of the light transmissive sheet.
  5. 5. The die package of claim 4 wherein the second passivation layer directly contacts the sidewall of the semiconductor substrate, the side of the bonding paste, the sidewall of the support, the sidewall of the transparent sheet and the top surface of the transparent sheet.
  6. 6. The wafer package of claim 3, wherein the light transmissive sheet further comprises: the two anti-reflection layers are respectively positioned on the top surface and the bottom surface of the light-transmitting sheet.
  7. 7. The die package of claim 6 wherein the second protective layer extends to the anti-reflective layer on the top surface of the light transmissive sheet.
  8. 8. The die package of claim 1 wherein the second protective layer directly contacts the sidewalls of the semiconductor substrate, the sides of the bond paste, and the support.
  9. 9. The die package of claim 1, wherein the material of the first protective layer is different from the material of the second protective layer, and the color of the first protective layer is different from the color of the second protective layer.
  10. 10. The die package of claim 1, wherein the semiconductor substrate has a through hole and the conductive pad is located in the through hole, the die package further comprising: an insulating layer on the wall surface of the through hole and the bottom surface of the semiconductor substrate; a rewiring layer on the conductive pad and the insulating layer, and And the under bump metal is positioned on the rewiring layer and the first protection layer.
  11. 11. The chip package of claim 10, wherein the material of the redistribution layer is copper and the material of the under bump metal comprises copper, nickel, and gold.
  12. 12. The die package of claim 10 wherein a portion of the ubm is located between the first and second passivation layers.
  13. 13. The die package recited in claim 10, further comprising: the conductive structure is located on the under bump metal and surrounded by the second protection layer.
  14. 14. A method for manufacturing a chip package is characterized by comprising the following steps: forming a trench on a top surface of a semiconductor substrate, wherein the top surface of the semiconductor substrate is provided with a conductive pad and a sensing area; bonding a support member to the top surface of the semiconductor substrate using a bonding adhesive, wherein the bonding adhesive is located in the trench, and the support member covers the bonding adhesive and surrounds the sensing region; forming a first protection layer on the bottom surface of the semiconductor substrate; Forming a dicing street between the semiconductor substrate and the support member, wherein the bonding adhesive is exposed from the dicing street, and Forming a second protection layer in the cutting channel and on the first protection layer, so that the second protection layer covers the first protection layer, the side wall of the semiconductor substrate and the side face of the bonding adhesive.
  15. 15. The method of claim 14, wherein the trench of the semiconductor substrate is formed by laser grooving.
  16. 16. The method of claim 14, wherein the dicing streets are formed between the semiconductor substrate and the supporting member such that corners of the bottom surface of the supporting member have notches.
  17. 17. The method of claim 16, wherein the second passivation layer is formed in the scribe line and on the first passivation layer such that the second passivation layer extends into the notch of the support.
  18. 18. The method of manufacturing a wafer package according to claim 14, further comprising: the support member is arranged on the bottom surface of the light transmitting sheet.
  19. 19. The method of claim 18, wherein the top surface of the light transmissive sheet is bonded to a carrier, the method further comprising: Cutting the second protective layer along the cutting path.
  20. 20. The method of claim 18, wherein the dicing streets are formed between the semiconductor substrate and the supporting member such that the streets extend into the transparent sheet.

Description

Chip package and method for manufacturing the same Technical Field The invention relates to a chip package and a manufacturing method of the chip package. Background Generally, a wafer package for image sensing includes a transparent sheet and a semiconductor substrate having a sensing region. In addition, the chip package may further include a redistribution layer, solder balls, and a protective layer (e.g., green paint). The passivation layer of the conventional chip package is only located on the bottom surface of the semiconductor substrate, for example, the passivation layer may be patterned to form an opening, and then a ball-mounting process is performed. However, the semiconductor substrate has no structure for preventing the transmission of stress, so that the stress may be transmitted to the inside of the semiconductor substrate during the manufacturing process of the chip package, resulting in damage. In addition, the side walls of the semiconductor substrate are exposed, so that moisture may intrude into the chip package from the edges of the semiconductor substrate, and noise light may also enter from the sides of the semiconductor substrate and the sides of the light-transmitting sheet. Therefore, the yield and reliability of the chip package are difficult to be improved, and the image sensing accuracy of the chip package is not facilitated. Disclosure of Invention According to some embodiments of the present invention, a chip package includes a semiconductor substrate, a bonding adhesive, a support, a first protective layer and a second protective layer. The top surface of the semiconductor substrate is provided with a conductive pad and a sensing area, and the corners of the top surface of the semiconductor substrate are provided with grooves. The bonding glue is located in the groove. The support piece covers the bonding adhesive and the conductive pad and surrounds the sensing area. The first protection layer is positioned on the bottom surface of the semiconductor substrate. The second protective layer covers the first protective layer, the side wall of the semiconductor substrate and the side face of the bonding adhesive. In some embodiments, the bottom surface of the support has a notch at a corner, and the second passivation layer extends into the notch. In some embodiments, the wafer package further comprises a light transmitting sheet. The light-transmitting sheet is positioned on the supporting piece and above the sensing area. In some embodiments, the second protective layer further covers the sidewall of the support, the sidewall of the light-transmitting sheet, and the top surface of the light-transmitting sheet. In some embodiments, the light-transmitting sheet further includes two anti-reflection layers, and the two anti-reflection layers are respectively located on the top surface and the bottom surface of the light-transmitting sheet. In some embodiments, the second protective layer extends to an anti-reflective layer on the top surface of the light transmissive sheet. In some embodiments, the second protective layer directly contacts the side wall of the semiconductor substrate, the side surface of the bonding adhesive, the side wall of the support, the side wall of the light transmitting sheet, and the top surface of the light transmitting sheet. In some embodiments, the second protective layer directly contacts the side wall of the semiconductor substrate, the side surface of the bonding adhesive and the support. In some embodiments, the material of the first protective layer is different from the material of the second protective layer, and the color of the first protective layer is different from the color of the second protective layer. In some embodiments, the semiconductor substrate has a through hole, and the conductive pad is located in the through hole, and the chip package further includes an insulating layer, a redistribution layer, and an under bump metal. The insulating layer is positioned on the wall surface of the through hole and the bottom surface of the semiconductor substrate. The rewiring layer is arranged on the conductive pad and the insulating layer. The under bump metal is located on the re-wiring layer and the first protection layer. In some embodiments, the material of the redistribution layer is copper, and the material of the under bump metal includes copper, nickel and gold. In some embodiments, a portion of the under bump metal is located between the first protective layer and the second protective layer. In some embodiments, the wafer package further includes a conductive structure. The conductive structure is located on the under bump metal and surrounded by the second protection layer. According to some embodiments of the present invention, a method for manufacturing a chip package includes forming a trench on a top surface of a semiconductor substrate, wherein the top surface of the semiconductor substrate has a conductive pad and a sensing