CN-122002940-A - Preparation method of silicon microstrip detector and silicon microstrip detector

CN122002940ACN 122002940 ACN122002940 ACN 122002940ACN-122002940-A

Abstract

The invention discloses a preparation method of a silicon microstrip detector and the silicon microstrip detector, relates to the technical field of semiconductor devices, and aims to solve the problem of low microstrip energy resolution of the silicon microstrip detector in the prior art. The method comprises the steps of providing a silicon substrate, sequentially depositing a first doping layer, a passivation layer and an electrode layer on the first surface of the silicon substrate, preprocessing the first doping layer, the passivation layer and the electrode layer to form a plurality of microstrip units and a plurality of guard ring units which are positioned on the silicon substrate, preprocessing the silicon substrate between a plurality of adjacent microstrip units to form a plurality of trench isolation units positioned in the silicon substrate to obtain a silicon microstrip detector, and reducing crosstalk between the microstrip units by using the trench isolation units based on the silicon microstrip detector, so that the microstrip energy resolution of the silicon microstrip detector is improved.

Inventors

JIA RUI
LI YONGYAO
LI XING
YUAN BINGQIAN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260508
Application Date: 20241104

Claims (10)

1. A method for manufacturing a silicon microstrip detector, comprising: Providing a silicon substrate; sequentially depositing a first doping layer, a passivation layer and an electrode layer on the first surface of the silicon substrate; preprocessing the first doping layer, the passivation layer and the electrode layer to form a plurality of microstrip units and a plurality of guard ring units which are positioned on the silicon substrate, wherein the plurality of guard ring units are positioned on the outer sides of the microstrip units; And preprocessing the silicon substrate between a plurality of adjacent microstrip units to form a plurality of trench isolation units positioned in the silicon substrate, thereby obtaining the silicon microstrip detector.
2. The method of claim 1, wherein the pre-processing the silicon substrate between the plurality of adjacent microstrip cells to form a plurality of trench isolation cells in the silicon substrate, comprises: Performing physical isolation on the silicon substrate between a plurality of adjacent microstrip units to obtain a plurality of intermediate trench isolation units; electrically isolating the plurality of intermediate trench isolation units to obtain a plurality of target trench isolation units with first doping layers; and taking a plurality of target trench isolation units as a plurality of trench isolation units positioned in the silicon substrate.
3. The method of claim 2, wherein said physically isolating the silicon substrate between a plurality of adjacent microstrip cells to obtain a plurality of intermediate trench isolation cells comprises: Etching the silicon substrate between a plurality of adjacent microstrip units by adopting a metal catalytic etching method to obtain a plurality of intermediate trench isolation units, wherein the metal comprises silver or copper; Or etching the silicon substrate between the adjacent microstrip units by adopting an alkali liquor etching method to obtain a plurality of intermediate trench isolation units, wherein the alkali liquor comprises KOH or NaOH solution, the etching temperature range is 20-90 ℃, and the concentration of the KOH or NaOH solution is 10-60%.
4. The method of claim 3, wherein etching the silicon substrate between the adjacent microstrip cells by metal-catalyzed etching to obtain a plurality of intermediate trench isolation cells comprises: etching the silicon substrate between a plurality of adjacent microstrip units by adopting a vacuum deposition method to obtain a plurality of intermediate trench isolation units; Or etching the silicon substrate between a plurality of adjacent microstrip units by adopting a metal wet process to obtain a plurality of intermediate trench isolation units.
5. The method of claim 4, wherein etching the silicon substrate between the plurality of adjacent microstrip cells using a wet metal process to obtain a plurality of intermediate trench isolation cells comprises: depositing a metal layer on a silicon substrate between a plurality of adjacent microstrip units by adopting a first mixture to obtain a plurality of metal layers, wherein the first mixture is obtained by mixing silver nitrate, hydrofluoric acid and water or copper sulfate, hydrofluoric acid and water according to a first proportion, and the first proportion is 1:5:200-3:7:240; Etching the silicon substrate by adopting a second mixture to obtain a plurality of first grooves, wherein the second mixture is obtained by mixing hydrofluoric acid, hydrogen peroxide and water according to a second proportion, and the second proportion is 47:160:270-43:40:116; Etching metal layers around the first grooves by using a third mixture to obtain a plurality of second grooves, wherein the third mixture is obtained by mixing ammonia water, hydrogen peroxide and water according to a third ratio, and the third ratio is 1:3:10-7:4:15; and performing roughness treatment on the second grooves by using a fourth mixture to obtain a plurality of middle groove isolation units, wherein the fourth mixture is a mixture obtained by mixing hydrofluoric acid, nitric acid and water according to a fourth proportion, and the fourth proportion is 80:54:116-72:100:124.
6. The method of claim 2, wherein a depth of the plurality of intermediate trench isolation cells is 1-100 μm and a width is 5-200 μm.
7. The method of claim 2, wherein the junction depth of the doped layers of the plurality of target trench isolation cells is 0.05-5 μm and the surface doping peak concentration is 1e 18 ～5e 20 /cm 3 .
8. The method of claim 1, wherein the silicon substrate comprises an N-type high-resistance silicon substrate or a P-type high-resistance silicon substrate, and wherein when the silicon substrate is an N-type high-resistance silicon substrate, the resistivity of the N-type high-resistance silicon substrate is 1000-20000 Ω -cm, and the thickness is 100-500 μm.
9. The silicon microstrip detector is characterized in that the silicon microstrip detector is manufactured by adopting the manufacturing method of the silicon microstrip detector as set forth in any one of claims 1 to 8, and the silicon microstrip detector comprises: A silicon substrate; the silicon substrate comprises a silicon substrate, a plurality of microstrip units, a plurality of guard ring units, a plurality of protective ring units and a plurality of protective ring units, wherein the microstrip units are arranged on the first surface of the silicon substrate; and the groove isolation units are arranged among a plurality of adjacent microstrip units and positioned in the silicon substrate to obtain the silicon microstrip detector.
10. The silicon microstrip detector as in claim 9 wherein a plurality of said microstrip cells comprises: The first doping layer is arranged on the first surface of the silicon substrate, the cross section width of the first doping layer is a first width, the passivation layer is arranged on the first doping layer far away from the first surface of the silicon substrate, the cross section width of the passivation layer is a first width, and the electrode layer is arranged on the passivation layer far away from the first doping layer, and the cross section width of the electrode layer is a first width; The plurality of guard ring units include: The first doping layer is arranged on the first surface of the silicon substrate, the cross section width of the first doping layer is a second width, the passivation layer is arranged on the first doping layer, far away from the first surface of the silicon substrate, the cross section width of the passivation layer is a second width, and the electrode layer is arranged on the passivation layer, far away from the first doping layer, and the cross section width of the electrode layer is a second width.

Description

Preparation method of silicon microstrip detector and silicon microstrip detector Technical Field The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a silicon microstrip detector and the silicon microstrip detector. Background Silicon microstrip detectors are widely used in the fields of high-energy physics experiments, space physics and cosmic ray science experiments, etc. due to their advantages of good position resolution, high energy resolution, very wide linear range, fast response time, etc. The silicon microstrip detector works on the principle that when the silicon microstrip detector works, reverse bias is applied to the back electrode so that the substrate is in a full depletion state, high-energy rays strike the incident window to form electron hole pairs, generated holes drift to the P-type doped layer along an electric field, electrons drift to the N-type doped layer, and then the electrons are collected by the front electrode and the back electrode. With the continuous development of the design and the continuous improvement of the performance of the silicon microstrip detector, the problem of the inter-microstrip crosstalk of the microstrip detector is more and more prominent, the inter-microstrip crosstalk characteristic can cause the generation of a charge sharing effect, so that the microstrip leakage current is increased, the problem of the microstrip energy resolution is further caused, and the application of the silicon microstrip detector in the fields of high-energy physical experiments, space physics, cosmic ray science experiments and the like is limited. Based on this, in order to improve the working performance of the silicon microstrip detector, it is necessary to design a technical scheme capable of improving and reducing the crosstalk characteristic of the silicon microstrip detector and ensuring the uniformity of microstrip leakage current so as to solve the problem of poor microstrip energy resolution of the silicon microstrip detector in the prior art. Disclosure of Invention The invention aims to provide a preparation method of a silicon microstrip detector and the silicon microstrip detector, which utilize trench isolation units arranged between adjacent microstrip units and positioned in a silicon substrate to reduce crosstalk characteristics among the microstrip units of the silicon microstrip detector, reduce capacitance and charge sharing effects among the microstrip units, and maintain uniformity of leakage current of the microstrip units, thereby improving microstrip energy resolution of the silicon microstrip detector and solving the problem of poor microstrip energy resolution of the silicon microstrip detector in the prior art. In order to achieve the above object, the present invention provides the following technical solutions: In a first aspect, the present invention provides a method for preparing a silicon microstrip detector, which may include: Providing a silicon substrate; sequentially depositing a first doping layer, a passivation layer and an electrode layer on the first surface of the silicon substrate; preprocessing the first doping layer, the passivation layer and the electrode layer to form a plurality of microstrip units and a plurality of guard ring units which are positioned on the silicon substrate, wherein the plurality of guard ring units are positioned on the outer sides of the microstrip units; And preprocessing the silicon substrate between a plurality of adjacent microstrip units to form a plurality of trench isolation units positioned in the silicon substrate, thereby obtaining the silicon microstrip detector. Preferably, the preprocessing the silicon substrate between the adjacent microstrip units to form a plurality of trench isolation units in the silicon substrate may include: Performing physical isolation on the silicon substrate between a plurality of adjacent microstrip units to obtain a plurality of intermediate trench isolation units; electrically isolating the plurality of intermediate trench isolation units to obtain a plurality of target trench isolation units with first doping layers; and taking a plurality of target trench isolation units as a plurality of trench isolation units positioned in the silicon substrate. Preferably, the physical isolation of the silicon substrate between the adjacent microstrip units to obtain a plurality of intermediate trench isolation units may include: Etching the silicon substrate between a plurality of adjacent microstrip units by adopting a metal catalytic etching method to obtain a plurality of intermediate trench isolation units, wherein the metal comprises silver or copper; Or etching the silicon substrate between the adjacent microstrip units by adopting an alkali liquor etching method to obtain a plurality of intermediate trench isolation units, wherein the alkali liquor comprises KOH or NaOH solution, the etching temperature