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CN-122002955-A - Heterojunction quantum well growth method and semiconductor device

CN122002955ACN 122002955 ACN122002955 ACN 122002955ACN-122002955-A

Abstract

The application provides a growth method of a heterojunction quantum well and a semiconductor device, wherein the method comprises the step of introducing HCl gas to perform interface treatment at least one selected key interface in the process of growing a heterojunction structure comprising a barrier layer and a quantum well layer by layer on a substrate by adopting a CVD process. The interface treatment is performed at a specific temperature, gas flow and time window to achieve chemical cleaning and/or passivation of the interface. Wherein the critical interfaces may include buffer layer surfaces, graded virtual substrate surfaces, and upper and lower interfaces of the quantum well layers. Through the controllable in-situ interface treatment, the application can effectively reduce the interface roughness and inhibit the mutual diffusion of components, thereby obtaining the heterojunction quantum well structure with steep interface and excellent quality. The semiconductor device prepared based on the method has the advantages that the roughness of the internal interface of the quantum well can be less than 0.5 nanometer, the thickness of the interface transition region can be less than 1 nanometer, and the semiconductor device is suitable for high-performance quantum computing, optical communication and photoelectric devices.

Inventors

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Assignees

  • 合肥国家实验室
  • 北京超弦存储器研究院

Dates

Publication Date
20260508
Application Date
20260408

Claims (10)

  1. 1. A method of growing heterojunction quantum wells, comprising: growing a heterojunction quantum well structure comprising a Si 1-x Ge x barrier layer and a quantum well layer by layer on a Si-based substrate by adopting a chemical vapor deposition method, wherein the quantum well layer is Si or Ge; During the layer-by-layer growth, an interface treatment with HCl gas is performed at least one interface selected from the group consisting of: The surface of the Ge buffer layer after the growth is completed, Si 1-x Ge x graded the surface of the virtual substrate after growth is completed, A bottom interface between the lower barrier layer and the quantum well layer, A top interface between the quantum well layer and an upper barrier layer; The interface process includes: And (3) introducing HCl gas at the treatment temperature of 400-690 ℃ to enable the HCl gas to be in contact with the interface, wherein the flow rate of the HCl gas is 2-150 sccm, and the treatment time is 2-120 seconds, so that the interface is chemically cleaned and/or passivated.
  2. 2. A growth method according to claim 1, wherein the interface treatment is performed in a single pass or at least two cycles.
  3. 3. A growth method according to claim 1, wherein the interface treatment is performed for each of the interfaces.
  4. 4. The growth method according to claim 1, wherein the interfacial treatment is performed with HCl gas in conjunction with an assist gas; The assist gas includes one or more of DCS, siH 4 , or GeH 4 .
  5. 5. The growth method according to claim 1, wherein the treatment temperature is 400 to 600 ℃, the HCl gas flow is 10 to 50sccm, and the treatment time is 30 to 120 seconds.
  6. 6. The growth method according to claim 1, wherein the processing temperature of the interface process is 500 ℃ for a bottom interface between a lower barrier layer and the quantum well layer and a top interface between the quantum well layer and an upper barrier layer.
  7. 7. The growth method according to claim 1, wherein the processing temperature of the interface process is 690 ℃ for the surface of the Si 1-x Ge x graded virtual substrate after the growth is completed.
  8. 8. A growth method according to any one of claims 1 to 7, comprising: Growing a Ge buffer layer on a Si-based substrate, and introducing the HCl gas to perform interface treatment on the surface of the Ge buffer layer; Epitaxially growing on the Ge buffer layer subjected to interface treatment to form a reverse graded Si 1-x Ge x graded virtual substrate, and introducing the HCl gas to perform interface treatment on the surface of the Si 1-x Ge x graded virtual substrate; On the Si 1-x Ge x gradual change virtual substrate subjected to interface treatment, epitaxially growing a Si 1-x Ge x lower barrier layer, a strained Ge quantum well layer and a Si 1-x Ge x upper barrier layer, and introducing HCl gas to perform interface treatment before and after the growth of the Ge quantum well layer; a Si cap layer is formed over the Si 1-x Ge x upper barrier layer.
  9. 9. A growth method according to any one of claims 1 to 7, comprising: Epitaxially growing on a Si-based substrate to form a Si 1-x Ge x gradient virtual substrate with forward gradient, and introducing the HCl gas to perform interface treatment on the surface of the Si 1-x Ge x gradient virtual substrate; Epitaxially growing a Si 1-x Ge x lower barrier layer, a strained Si quantum well layer and a Si 1-x Ge x upper barrier layer on the Si 1-x Ge x gradient virtual substrate subjected to the interface treatment, and introducing the HCl gas to perform the interface treatment before and after the growth of the Si quantum well layer; a Si cap layer is formed over the Si 1-x Ge x upper barrier layer.
  10. 10. A semiconductor device, characterized in that the manufacturing method of the semiconductor device comprises the growth method of the heterojunction quantum well as claimed in any one of claims 1 to 9; in the heterojunction quantum well stacking structure of the semiconductor device, the roughness of each inner interface is smaller than 0.5nm, and the thickness of a transition region is smaller than 1nm; The semiconductor device is applied to quantum computing, optical communication or as an optoelectronic device.

Description

Heterojunction quantum well growth method and semiconductor device Technical Field The application relates to the technical field of chemical vapor deposition (Chemical Vapor Deposition, CVD), in particular to a growth method of a heterojunction quantum well and a semiconductor device obtained by adopting the growth method. Background In the field of semiconductor devices, a quantum well structure based on a GeSi heterojunction is one of core materials for constructing high-performance photoelectrons and quantum devices. The performance of the device is greatly dependent on the abruptness and flatness of the heterojunction interface. Currently, when Chemical Vapor Deposition (CVD) technology is adopted to grow the structure, technical challenges such as difficulty in controlling atomic level flatness of a growing interface, wide transition area of an interface component caused by interdiffusion of Si/Ge elements and the like are commonly faced. These imperfect interfaces can introduce scattering centers, impair quantum confinement effects, lead to reduced carrier mobility and unstable device performance. The existing technical schemes for improving the interface quality, such as fine control of growth kinetic parameters or high-temperature cleaning, are difficult to achieve balance between inhibiting the inter-diffusion of atoms and ensuring good crystal quality. In particular, when growing complex quantum well stack structures comprising a plurality of heterogeneous interfaces, there is a lack of efficient and controllable process means how to ensure that a high quality and consistent process is obtained for each interface from the substrate to the top layer. Therefore, a new method for optimizing the chemical state and morphology of a specific heterojunction interface in situ and selectively in a conventional CVD growth temperature range is urgently needed, so that the limitation of the existing interface control technology is broken through, and the reliable preparation of a high-quality GeSi quantum well structure is realized. Disclosure of Invention The application aims to solve the problem of poor interface quality when a GeSi heterojunction quantum well grows by the existing chemical vapor deposition method, and particularly comprises the steps of effectively reducing the surface roughness of the heterojunction interface, inhibiting the interdiffusion among Si/Ge atoms to obtain a steep component transition interface and realizing in-situ, consistent and controllable optimization treatment on a plurality of key interfaces when a multilayer quantum well structure grows. In view of the foregoing, the present application provides a method for growing heterojunction quantum wells and a semiconductor device. In a first aspect, the present application provides a method for growing heterojunction quantum wells, comprising: And growing the heterojunction quantum well structure containing the Si 1-xGex barrier layer and the quantum well layer by layer on the Si-based substrate by adopting a chemical vapor deposition method, wherein the quantum well layer is Si or Ge. And introducing HCl gas at least one key interface in the process of layer-by-layer growth for interface treatment. The key interfaces comprise a surface after the growth of the Ge buffer layer is completed, a surface after the growth of the Si 1-xGex graded virtual substrate is completed, a bottom interface between the lower barrier layer and the quantum well layer, and a top interface between the quantum well layer and the upper barrier layer. The interface treatment comprises the steps of introducing HCl gas with the flow rate of 2-150 sccm into a reaction chamber at the treatment temperature of 400-690 ℃ to enable the HCl gas to be in contact with the interface, and carrying out chemical cleaning and/or passivation on the interface for 2-120 seconds. Alternatively, the interface treatment may be performed in a single pass or may be repeated at least twice. Optionally, the HCl gas interface treatment is performed on each of the critical interfaces in the heterojunction structure. Optionally, the interface treatment may be performed by co-introducing an auxiliary gas including one or more of Dichlorosilane (DCS), silane (SiH 4) or germane (GeH 4) while introducing HCl gas. Alternatively, a preferred set of process parameters is a process temperature in the range of 400 ℃ to 600 ℃, a HCl gas flow in the range of 10sccm to 50sccm, and a process time in the range of 30 seconds to 120 seconds. Optionally, the processing temperature of the interface processing is 500 ℃ for a bottom interface between the lower barrier layer and the quantum well layer, and a top interface between the quantum well layer and the upper barrier layer. Alternatively, the processing temperature of the interface process is 690 ℃ for the surface of the Si 1-xGex graded virtual substrate after growth is completed. Optionally, one specific embodiment of the method includes: gro