CN-122002978-A - Semiconductor chip and method for manufacturing the same

Abstract

The disclosure discloses a semiconductor chip and a preparation method thereof, and belongs to the technical field of semiconductors. The semiconductor chip comprises an epitaxial layer and a passivation layer, wherein the passivation layer comprises a buffer layer, a gradual change layer and a covering layer which are sequentially overlapped on one surface of the epitaxial layer, and the overlapping direction of the buffer layer, the gradual change layer and the covering layer is the growth direction of the epitaxial layer. According to the embodiment of the disclosure, the epitaxial layer can be effectively protected from being damaged under the condition of ensuring the luminous efficiency.

Inventors

• CONG YING
• YAO ZHEN

Assignees

• 京东方华灿光电(苏州)有限公司

Dates

Publication Date

20260508

Application Date

20251222

Claims (10)

1. 1. A semiconductor chip, characterized by comprising an epitaxial layer (10) and a passivation layer (20); the passivation layer (20) comprises a buffer layer (210), a gradual change layer (220) and a covering layer (230) which are sequentially stacked on one surface of the epitaxial layer (10), and the stacking direction of the buffer layer (210), the gradual change layer (220) and the covering layer (230) is the growth direction of the epitaxial layer (10).
2. 2. The semiconductor chip according to claim 1, wherein the buffer layer (210) is a ZnO layer, the graded layer (220) is a ZnMgO layer, and the cap layer (230) is a MgO layer.
3. 3. The semiconductor chip according to claim 1 or 2, wherein the thickness of the buffer layer (210) is 3-5 nm; the buffer layer (210) comprises a plurality of buffer sublayers (211) which are stacked in sequence, the buffer sublayers (211) are ZnO layers, and the number of the buffer sublayers (211) is 15-25.
4. 4. The semiconductor chip according to claim 1 or 2, wherein the graded layer (220) comprises a plurality of sequentially stacked cyclic groups (221); each circulation group (221) comprises a plurality of gradual change sublayers (222), the gradual change sublayers (222) are ZnO layers or MgO layers, the gradual change sublayers (222) are sequentially stacked, and the number of the circulation groups (221) is 80-120; the thickness of one circulation group (221) is 0.15-0.3 nm, and the thickness of the gradual change layer (220) is 18-25 nm.
5. 5. The semiconductor chip according to claim 4, wherein the number of the graded sublayers (222) of the ZnO layer in each of the cyclic groups (221) gradually decreases and the number of the graded sublayers (222) of the MgO layer in each of the cyclic groups (221) gradually increases along the growth direction of the epitaxial layer (10).
6. 6. The semiconductor chip according to claim 1 or 2, wherein the thickness of the cover layer (230) is 1.5-3 nm; The covering layer (230) comprises a plurality of covering sub-layers (231) which are sequentially stacked, the covering sub-layers (231) are MgO layers, and the number of the covering sub-layers (231) is 8-12.
7. 7. A method of manufacturing a semiconductor chip, comprising: Preparing an epitaxial layer (10); And preparing a buffer layer (210), a graded layer (220) and a cover layer (230) on one side of the epitaxial layer (10) in sequence to obtain a passivation layer (20).
8. 8. The method of manufacturing according to claim 7, wherein manufacturing the buffer layer (210) comprises: Setting the preparation temperature to 130-160 ℃, and starting a Zn source and an O source; growing a buffer sub-layer (211) at a rate of 0.15-0.3 nm/layer to obtain 15-25 layers of the buffer sub-layer (211); the buffer sub-layers (211) are stacked to obtain the buffer layer (210), and the buffer layer (210) is a ZnO layer.
9. 9. The method of manufacturing according to claim 7, wherein preparing the graded layer (220) comprises: Setting the preparation temperature to 130-160 ℃; starting a Zn source, an Mg source and an O source, and sequentially growing 80-120 gradual change sublayers (222), wherein the gradual change sublayers (222) are ZnO layers or MgO layers; The graded sublayers (222) form a cycle group (221) so as to obtain a plurality of cycle groups (221), the number of the graded sublayers (222) with ZnO layers in each cycle group (221) gradually decreases, and the number of the graded sublayers (222) with MgO layers in each cycle group (221) gradually increases along the growth direction of the epitaxial layer (10); And stacking a plurality of circulating groups (221) to obtain the graded layer (220), wherein the graded layer (220) is a ZnMgO layer.
10. 10. The method of preparing according to claim 7, characterized in that preparing the cover layer (230) comprises: setting the preparation temperature to 130-160 ℃, and starting an Mg source and an O source; sequentially growing 8-12 covering sub-layers (231); the cover layer (230) is obtained by stacking a plurality of cover sub-layers (231), and the cover layer (230) is an MgO layer.

Description

Semiconductor chip and method for manufacturing the same Technical Field The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor chip and a preparation method thereof. Background A Micro LED (Micro LIGHT EMITTING Diode) chip is a semiconductor chip with a very small size. In the related art, the semiconductor chip mainly includes an epitaxial layer, and a mesa etching process is required to be performed on the semiconductor chip during the manufacturing process. However, since the semiconductor chip is very small in size and has a very large ratio of the area to the volume of the side wall, lattice damage is easily caused to the active layer in the epitaxial layer when the mesa etching process is performed, and then a side wall defect occurs, which becomes a main center of carrier non-radiative recombination, resulting in a drastic decrease in the light emitting efficiency of the semiconductor chip. In order to solve the above problems, a passivation layer of SiO 2 is covered outside the epitaxial layer in the related art, so as to protect the epitaxial layer. However, since the SiO 2 passivation layer is lattice mismatched with the GaN epitaxial layer, a high density of interface states may be generated, resulting in an influence on light emitting efficiency. Disclosure of Invention The embodiment of the disclosure provides a semiconductor chip and a preparation method thereof, which can effectively protect an epitaxial layer from being damaged under the condition of ensuring luminous efficiency. The technical scheme is as follows: In one aspect, embodiments of the present disclosure provide a semiconductor chip including an epitaxial layer and a passivation layer; the passivation layer comprises a buffer layer, a gradual change layer and a covering layer which are sequentially overlapped on one surface of the epitaxial layer, and the overlapping direction of the buffer layer, the gradual change layer and the covering layer is the growth direction of the epitaxial layer. In one implementation of the present disclosure, the buffer layer is a ZnO layer, the graded layer is a ZnMgO layer, and the capping layer is a MgO layer. In one implementation of the disclosure, the thickness of the buffer layer is 3-5 nm; the buffer layer comprises a plurality of buffer sublayers which are sequentially stacked, the buffer sublayers are ZnO layers, and the number of the buffer sublayers is 15-25. In one implementation of the present disclosure, the graded layer includes a plurality of cyclic groups stacked in sequence; Each circulation group comprises a plurality of gradual change sublayers, the gradual change sublayers are ZnO layers or MgO layers, the gradual change sublayers are sequentially stacked, and the number of the circulation groups is 80-120; The thickness of one circulation group is 0.15-0.3 nm, and the thickness of the gradual change layer is 18-25 nm. In one implementation of the present disclosure, the number of the graded sublayers of the ZnO layer in each of the cyclic groups gradually decreases and the number of the graded sublayers of the MgO layer in each of the cyclic groups gradually increases along the growth direction of the epitaxial layer. In one implementation of the disclosure, the thickness of the cover layer is 1.5-3 nm; the covering layer comprises a plurality of covering sub-layers which are sequentially stacked, wherein the covering sub-layers are MgO layers, and the number of the covering sub-layers is 8-12. In another aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor chip, including: Preparing an epitaxial layer; And sequentially preparing a buffer layer, a gradual change layer and a covering layer on one side of the epitaxial layer to obtain a passivation layer. In one implementation of the present disclosure, preparing the buffer layer includes: Setting the preparation temperature to 130-160 ℃, and starting a Zn source and an O source; Growing a buffer sub-layer at a rate of 0.15-0.3 nm/layer to obtain 15-25 layers of buffer sub-layers; And stacking a plurality of buffer sublayers to obtain the buffer layer, wherein the buffer layer is a ZnO layer. In one implementation of the present disclosure, preparing a graded layer includes: Setting the preparation temperature to 130-160 ℃; Starting a Zn source, an Mg source and an O source, and sequentially growing 80-120 gradual change sublayers, wherein the gradual change sublayers are ZnO layers or MgO layers; The graded sublayers are combined into a circulation group to obtain a plurality of circulation groups, the number of the graded sublayers with the ZnO layer in each circulation group is gradually reduced, and the number of the graded sublayers with the MgO layer in each circulation group is gradually increased along the growth direction of the epitaxial layer; and stacking a plurality of the circulating groups to obtain the graded l