CN-122002992-A - HEMT integrated light-emitting chip, preparation method thereof, epitaxial wafer and display backboard

CN122002992ACN 122002992 ACN122002992 ACN 122002992ACN-122002992-A

Abstract

The application discloses a HEMT integrated light-emitting chip and a preparation method thereof, an epitaxial wafer and a display backboard, wherein the method comprises the steps of providing a HEMT integrated epitaxial wafer, wherein the HEMT integrated epitaxial wafer comprises a three-color quantum well lamination, and the three-color quantum well lamination comprises a primary first quantum well layer, a primary second quantum well layer and a primary third quantum well layer which are laminated in sequence and the energy band width of the primary first quantum well layer, the primary second quantum well layer and the primary third quantum well layer is reduced in sequence; etching the three-color quantum well lamination to form a first quantum well layer, a second quantum well layer laminated on the first quantum well layer and a third quantum well layer laminated on the second quantum well layer, sequentially growing barrier layers and P-type semiconductor layers and etching to form barrier layers and P-type semiconductor layers corresponding to the quantum wells, etching electrode holes, growing electrode layers and etching to form corresponding source electrodes, drain electrodes and common drain electrodes. According to the HEMT integrated light-emitting chip and the preparation method thereof, the HEMT structure is utilized to prepare the two-dimensional electron gas in the well, so that the electron migration efficiency is greatly improved, and single-color, double-color and three-color display can be realized.

Inventors

WEI SHENGLONG
DONG HONGWEI
Xun Likai
TANG YUYING
CHEN XIAOFENG

Assignees

重庆康佳光电科技有限公司

Dates

Publication Date: 20260508
Application Date: 20241101

Claims (17)

1. The HEMT integrated light-emitting chip is characterized by comprising an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer, a second quantum well layer and a third quantum well layer which are sequentially stacked from bottom to top, wherein the light-emitting colors of the first quantum well layer, the second quantum well layer and the third quantum well layer are different, and the energy bandwidths of the first quantum well layer, the second quantum well layer and the third quantum well layer are sequentially reduced; The first quantum well layer comprises a first light-emitting region, a second light-emitting region and a third light-emitting region, the second quantum well layer is arranged on the second light-emitting region and the third light-emitting region, the third quantum well layer is arranged on the second quantum well layer corresponding to the third light-emitting region, a first barrier layer and a first P-type semiconductor layer are sequentially stacked on the first light-emitting region, a first source electrode connected with the first P-type semiconductor layer is arranged on the first P-type semiconductor layer, a first grid electrode arranged on the first barrier layer and arranged at intervals with the first P-type semiconductor layer, a second barrier layer and a second P-type semiconductor layer are sequentially stacked on the second quantum well layer corresponding to the second light-emitting region, a second source electrode connected with the second P-type semiconductor layer is arranged on the second barrier layer, a second barrier layer is arranged on the second P-type semiconductor layer and is connected with the third P-type semiconductor layer, a third barrier layer is sequentially stacked on the third P-type semiconductor layer and the third P-type semiconductor layer is arranged on the third barrier layer, and the third P-type semiconductor layer is sequentially stacked on the third quantum well layer is connected with the third P-type semiconductor layer, and the third P-type semiconductor layer is sequentially arranged on the third barrier layer is arranged on the third P-type semiconductor layer.
2. The HEMT integrated light-emitting chip of claim 1, wherein said second quantum well layer on said second light-emitting region and said second quantum well layer on said third light-emitting region are disposed apart.
3. The HEMT integrated light-emitting chip of claim 2, wherein the first quantum well layer corresponding to the first light-emitting region, the first quantum well layer corresponding to the second light-emitting region, and the first quantum well layer corresponding to the third light-emitting region are disposed apart.
4. The HEMT-integrated light-emitting chip of any one of claims 1-3, wherein each of the first quantum well layer, the second quantum well layer, and the third quantum well layer comprises at least one of an In-doped InGaN layer, an Al-doped AlGaN layer, an undoped GaN layer, an Al-doped, in-doped AlInGaN layer.
5. The HEMT integrated light-emitting chip of claim 4, wherein the first quantum well layer, the second quantum well layer, and the third quantum well layer are all In-doped InGaN layers, wherein the first quantum well layer is a blue light quantum well layer, wherein the second quantum well layer is a green light quantum well layer, wherein the third quantum well layer is a red light quantum well layer, and wherein In-doping contents of the first quantum well layer, the second quantum well layer, and the third quantum well layer are sequentially increased.
6. The HEMT-integrated light-emitting chip of claim 5, wherein the first barrier layer, the second barrier layer, and the third barrier layer each comprise at least one of an AlN barrier layer and an AlGaN barrier layer.
7. The HEMT integrated light-emitting chip of claim 6, wherein the first barrier layer, the second barrier layer, and the third barrier layer are all Al-doped AlGaN barrier layers.
8. The HEMT integrated light-emitting chip of claim 7, wherein said N-type semiconductor layer comprises at least one of an N-type GaN layer and an N-type AlGaN layer; The first P-type semiconductor layer, the second P-type semiconductor layer and the third P-type semiconductor layer are the same in material, and the first P-type semiconductor layer comprises at least one of a P-type GaN layer and a P-type AlGaN layer.
9. The HEMT integrated light-emitting chip of claim 7, further comprising a substrate, a nucleation layer, and a buffer layer, wherein the buffer layer, the nucleation layer, and the substrate are sequentially stacked on a side of the N-type semiconductor layer remote from the intrinsic semiconductor layer.
10. A HEMT integrated epitaxial wafer for preparing the HEMT integrated light-emitting chip according to any one of claims 1 to 9, comprising a substrate, a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer and a three-color quantum well stack layer which are sequentially stacked from bottom to top, wherein the three-color quantum well stack layer comprises a primary first quantum well layer, a primary second quantum well layer and a primary third quantum well layer which are sequentially overlapped on the intrinsic semiconductor layer, and the energy bandwidths of the primary first quantum well layer, the primary second quantum well layer and the primary third quantum well layer are sequentially reduced.
11. The HEMT-integrated epitaxial wafer of claim 10, wherein said growing a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer, and a three-color quantum well stack in this order from bottom to top on the surface of said substrate comprises performing the steps of: Growing the nucleation layer with a first preset thickness on the surface of the substrate at a first preset temperature and a first preset pressure; Growing the buffer layer with a second preset thickness on the surface of the nucleation layer at a second preset temperature and a second preset pressure; Growing the N-type semiconductor layer with a third preset thickness on the surface of the buffer layer at a third preset temperature and a third preset pressure; growing a fourth preset thickness of the intrinsic semiconductor layer on the surface of the N-type semiconductor layer at a fourth preset temperature and a fourth preset pressure; Growing the original first quantum well layer with a fifth preset thickness on the surface of the intrinsic semiconductor layer at a fifth preset temperature and a fifth preset pressure; Growing a sixth preset thickness of the original second quantum well layer on the surface of the first quantum well layer at a sixth preset temperature and a sixth preset pressure; Growing the original third quantum well layer with a seventh preset thickness on the surface of the second quantum well layer at a seventh preset temperature and a seventh preset pressure; The step of sequentially growing the barrier layer and the P-type semiconductor layer comprises the following steps: Growing the barrier layer with the eighth preset thickness on the etched epitaxial wafer at the eighth preset temperature and the eighth preset pressure; and growing the P-type semiconductor layer with the ninth preset thickness on the surface of the barrier layer at the ninth preset temperature and the ninth preset pressure.
12. The HEMT-integrated epitaxial wafer of claim 10, wherein the material types of the primary first quantum well layer, the primary second quantum well layer, and the primary third quantum well layer are the same.
13. A method for manufacturing the HEMT-integrated light-emitting chip according to any one of claims 1 to 9, characterized by comprising the steps of: Providing a HEMT-integrated epitaxial wafer according to any one of claims 10 to 12, wherein the HEMT-integrated epitaxial wafer comprises a substrate, a nucleation layer, a buffer layer, an N-type semiconductor layer, an intrinsic semiconductor layer and a three-color quantum well stack which are sequentially stacked from bottom to top, wherein the three-color quantum well stack comprises a primary first quantum well layer, a primary second quantum well layer and a primary third quantum well layer which are sequentially overlapped on the intrinsic semiconductor layer, and the energy bandwidths of the primary first quantum well layer, the primary second quantum well layer and the primary third quantum well layer are sequentially reduced; Etching the three-color quantum well lamination to form a first quantum well layer, a second quantum well layer laminated on the first quantum well layer and a third quantum well layer laminated on the second quantum well layer, wherein the first quantum well layer comprises a first light-emitting area, a second light-emitting area and a third light-emitting area, the second quantum well layer is arranged on the second light-emitting area and the third light-emitting area, and the third quantum well layer is arranged on the second quantum well layer corresponding to the third light-emitting area; Sequentially growing a barrier layer and a P-type semiconductor layer; Sequentially etching the P-type semiconductor layer and the barrier layer to form a first barrier layer and a first P-type semiconductor layer sequentially stacked on the first light emitting region, a second barrier layer and a second P-type semiconductor layer sequentially stacked on the second quantum well layer corresponding to the second light emitting region, and a third barrier layer and a third P-type semiconductor layer sequentially stacked on the third quantum well layer; Etching the exposed first quantum well layer and the intrinsic semiconductor layer until the N-type semiconductor layer is exposed, and forming an electrode hole; Growing electrode layers on the epitaxial wafer after the electrode hole etching is completed and in the electrode hole; The electrode layer is etched to form a first source electrode, a second source electrode and a third source electrode which are respectively arranged on the first P-type semiconductor layer, the second P-type semiconductor layer and the third P-type semiconductor layer, a first grid electrode, a second grid electrode and a third grid electrode which are respectively arranged on the first barrier layer, the second barrier layer and the third barrier layer, and a common drain electrode which is connected with the N-type semiconductor layer and extends along the direction of the first quantum well layer, wherein the first source electrode is connected with the first P-type semiconductor layer, the first grid electrode is arranged at intervals with the first P-type semiconductor layer, the second source electrode is connected with the second P-type semiconductor layer, the second grid electrode is arranged at intervals with the second P-type semiconductor layer, the third source electrode is connected with the third P-type semiconductor layer, and the third grid electrode is arranged at intervals with the third P-type semiconductor layer, so that the HEMT integrated luminous chip is obtained.
14. The method of manufacturing a HEMT integrated light-emitting chip of claim 13, wherein said etching said three-color quantum well stack forms a first quantum well layer, a second quantum well layer stacked on said first quantum well layer, and a third quantum well layer stacked on said second quantum well layer, said first quantum well layer including a first light-emitting region, a second light-emitting region, and a third light-emitting region, said second quantum well layer being disposed on said second light-emitting region and said third light-emitting region, said third quantum well layer being disposed on said second quantum well layer corresponding to said third light-emitting region, comprising the steps of: Etching the original third quantum well layer until reaching the original second quantum well layer to obtain a third quantum well layer laminated on the original second quantum well layer; etching the original second quantum well layer between the second light-emitting region and the third light-emitting region until reaching the original first quantum well layer, so that the second quantum well layer on the second light-emitting region and the second quantum well layer on the third light-emitting region are arranged at intervals.
15. The method for manufacturing a HEMT integrated light-emitting chip according to claim 14, wherein after said etching of said original second quantum well layer between said second light-emitting region and said third light-emitting region to an original first quantum well layer such that said second quantum well layer on said second light-emitting region and said second quantum well layer on said third light-emitting region are spaced apart, further comprising the steps of: Etching the original first quantum well layer between the first light emitting region and the second light emitting region, the original first quantum well layer between the second light emitting region and the third light emitting region, and the original first quantum well layer between the first light emitting region and the third light emitting region, so that the first quantum well layer corresponding to the first light emitting region, the first quantum well layer corresponding to the second light emitting region, and the first quantum well layer corresponding to the third light emitting region are arranged at intervals.
16. The method according to any one of claims 13 to 15, wherein, after etching the electrode layer, a first source, a second source, and a third source respectively provided on the first P-type semiconductor layer, the second P-type semiconductor layer, and the third P-type semiconductor layer, a first gate, a second gate, and a third gate respectively provided on the first barrier layer, the second barrier layer, and the third barrier layer, and a common drain connected to the N-type semiconductor layer and extending in the direction of the first quantum well layer are formed, the first source is connected to the first P-type semiconductor layer, the first gate is spaced apart from the first P-type semiconductor layer, the second source is connected to the second P-type semiconductor layer, the second gate is spaced apart from the second P-type semiconductor layer, the third source is connected to the third P-type semiconductor layer, and the third gate is spaced apart from the third P-type semiconductor layer, and the following the steps are further included: the buffer layer is decomposed to peel off the substrate.
17. A display back plate comprising a drive substrate and the HEMT-integrated light-emitting chip according to any one of claims 1 to 9 bonded to the drive substrate.

Description

HEMT integrated light-emitting chip, preparation method thereof, epitaxial wafer and display backboard Technical Field The application relates to the field of display, in particular to an HEMT integrated light emitting chip and a preparation method thereof, an epitaxial wafer and a display backboard. Background HEMT (High Electron Mobility Transistor) and LED (LIGHT EMITTING Diode) have great potential and wide application fields as devices having important applications in the electronic and optoelectronic fields. HEMTs are high electron mobility transistors that have excellent performance in high frequency and microwave circuits, and are commonly used in radio frequency power amplifiers and microwave receivers. An LED is a semiconductor device capable of converting electric energy into light energy, and is widely used in the fields of lighting, display screens, and communication. In recent years, with the development of electronic and optoelectronic integration technology, how to apply HEMTs to MicroLED is a difficulty in the art. The chinese patent document CN117153961a discloses a HEMT-driven MicroLED integrated back plate and a method for manufacturing the same, the method steps include growing HEMT epitaxial structures on a substrate, sequentially growing three single-color LED epitaxial structures on the HEMT epitaxial structures to obtain epitaxial wafers, etching to the substrate-to-epitaxial wafer partition, depositing passivation layers, etching through holes, and then depositing conductors to connect n-GaN layers of three LED regions to one HEMT region, and connecting the remaining three HEMT regions to p-GaN layers of one LED region. The method integrates the HEMT and the three-color LED device on a single substrate at an epitaxial end, and is a design for applying the HEMT to MicroLED display fields. Disclosure of Invention In view of the shortcomings of the related art, the application aims to provide an HEMT integrated light-emitting chip, a preparation method thereof, an epitaxial wafer and a display backboard, which are used for realizing the combination of an HEMT structure and an LED, are more compact in structure, and utilize the HEMT structure to prepare two-dimensional electron gas in a well, so that the electron migration efficiency is greatly improved, the number of electrons and holes which emit light in an active area is improved, the starting voltage is reduced, the light-emitting brightness is improved, and the single-color, double-color and three-color display can be realized. The application provides an HEMT integrated light-emitting chip, which comprises an N-type semiconductor layer, an intrinsic semiconductor layer, a first quantum well layer, a second quantum well layer and a third quantum well layer which are sequentially stacked from bottom to top, wherein the light-emitting colors of the first quantum well layer, the second quantum well layer and the third quantum well layer are different, and the energy bandwidths of the first quantum well layer, the second quantum well layer and the third quantum well layer are sequentially reduced; The first quantum well layer comprises a first light-emitting region, a second light-emitting region and a third light-emitting region, the second quantum well layer is arranged on the second light-emitting region and the third light-emitting region, the third quantum well layer is arranged on the second quantum well layer corresponding to the third light-emitting region, a first barrier layer and a first P-type semiconductor layer are sequentially stacked on the first light-emitting region, a first source electrode connected with the first P-type semiconductor layer is arranged on the first P-type semiconductor layer, a first grid electrode arranged on the first barrier layer and arranged at intervals with the first P-type semiconductor layer, a second barrier layer and a second P-type semiconductor layer are sequentially stacked on the second quantum well layer corresponding to the second light-emitting region, a second source electrode connected with the second P-type semiconductor layer is arranged on the second barrier layer, a second barrier layer is arranged on the second P-type semiconductor layer and is connected with the third P-type semiconductor layer, a third barrier layer is sequentially stacked on the third P-type semiconductor layer and the third P-type semiconductor layer is arranged on the third barrier layer, and the third P-type semiconductor layer is sequentially stacked on the third quantum well layer is connected with the third P-type semiconductor layer, and the third P-type semiconductor layer is sequentially arranged on the third barrier layer is arranged on the third P-type semiconductor layer. Optionally, the second quantum well layer on the second light emitting region and the second quantum well layer on the third light emitting region are spaced apart. Optionally, the first quantum well layer corresponding to