CN-122003032-A - Display panel and electronic device comprising same

CN122003032ACN 122003032 ACN122003032 ACN 122003032ACN-122003032-A

Abstract

The application discloses a display panel and an electronic device comprising the same. The display panel includes a base substrate, a semiconductor pattern, an insulating layer, a gate pattern, an interlayer insulating layer, a source-drain pattern, a via layer, and a light emitting diode. The base substrate includes a first region and a second region, the second region including a bending region being bendable, a cover region extending from one side of the bending region and surrounding the first region, and a pad region extending from an opposite side of the bending region from the one side of the bending region. The semiconductor pattern on the first region includes a semiconductor material. An insulating layer on the base substrate covers the semiconductor pattern. The gate pattern on the gate insulating layer at least partially overlaps the semiconductor pattern. The insulating layer covers the gate pattern. A first crack stop opening and a second crack stop opening are defined in the insulating layer. The number of first crack stop openings is different from the number of second crack stop openings.

Inventors

Zheng Xuanjiao
SONG HAOCHENG
CAO CHENGMIN

Assignees

三星显示有限公司

Dates

Publication Date: 20260508
Application Date: 20251023
Priority Date: 20241101

Claims (10)

1. A display panel, comprising: A base substrate including a first region and a second region, the second region including a bending region being bendable, a cover region extending from one side of the bending region and surrounding the first region, and a pad region extending from an opposite side of the bending region from the one side of the bending region; A semiconductor pattern disposed on the first region and including a semiconductor material; a gate insulating layer disposed on the base substrate and covering the semiconductor pattern; A gate pattern disposed on the gate insulating layer and including at least a portion overlapping the semiconductor pattern; an interlayer insulating layer covering the gate pattern; a source-drain pattern disposed on the interlayer insulating layer and including at least a portion electrically connected to the semiconductor pattern; a via layer covering the source-drain pattern, and A light emitting diode arranged on the through hole layer, Wherein a plurality of first crack stop openings each extending along an outer edge of the cap region are defined in a portion of the interlayer insulating layer overlapping the cap region, A plurality of second crack stop openings each extending along an outer edge of the pad region are defined in a portion of the interlayer insulating layer overlapping the pad region, and The number of the plurality of first crack stop openings and the number of the plurality of second crack stop openings are different from each other.
2. The display panel of claim 1, wherein the number of the plurality of second crack stop openings is greater than the number of the plurality of first crack stop openings.
3. The display panel of claim 2, wherein at least one of a plurality of third crack stop openings and a plurality of fourth crack stop openings are defined in the gate insulating layer, wherein the plurality of third crack stop openings overlap the plurality of first crack stop openings, respectively, and the plurality of fourth crack stop openings overlap the plurality of second crack stop openings, respectively.
4. The display panel of claim 3, further comprising: a plurality of pads disposed on the pad region; an electrical component overlapping the plurality of pads, and A plurality of spider wiring lines extending from the plurality of pads, respectively, and configured to transmit signals provided by the electrical component to at least one of the source-drain pattern and the gate pattern, Wherein the plurality of second crack stop openings are defined between the plurality of spider wiring lines and the outer edge of the pad area.
5. The display panel of claim 4, wherein the plurality of second crack stop openings are spaced apart from the plurality of first crack stop openings across the bending zone in plan view.
6. The display panel of claim 4, wherein the plurality of second crack stop openings overlap at least one of the first region and the overlay region when the bend region is bent.
7. The display panel of claim 4, wherein the base substrate comprises: a first substrate layer comprising an organic material; A second substrate layer disposed on the first substrate layer, and A third substrate layer disposed on the second substrate layer and comprising an organic material, At least one of a plurality of fifth crack stop openings and a plurality of sixth crack stop openings are defined in the second substrate layer, The plurality of fifth crack stop openings overlap with the plurality of first crack stop openings, respectively, and The plurality of sixth crack stop openings overlap the plurality of second crack stop openings, respectively.
8. The display panel of claim 4, wherein the shape formed by projecting each of the plurality of second crack stop openings onto the base substrate comprises at least one of a straight shape, a curved shape, and a zigzag shape.
9. The display panel of claim 4, further comprising: a functional layer disposed between the base substrate and the semiconductor pattern, Wherein at least one of a plurality of seventh crack stop openings and a plurality of eighth crack stop openings is defined in the functional layer, The plurality of seventh crack stop openings overlap with the plurality of first crack stop openings, respectively, and The plurality of eighth crack stop openings overlap the plurality of second crack stop openings, respectively.
10. An electronic device, comprising: a display panel, comprising: A base substrate including a first region and a second region, the second region including a bending region being bendable, a cover region extending from one side of the bending region and surrounding the first region, and a pad region extending from an opposite side of the bending region from the one side of the bending region; A semiconductor pattern disposed on the first region and including a semiconductor material; a gate insulating layer disposed on the base substrate and covering the semiconductor pattern; A gate pattern disposed on the gate insulating layer and including at least a portion overlapping the semiconductor pattern; an interlayer insulating layer covering the gate pattern and including a plurality of first protruding members spaced apart from each other on the cover region, and a plurality of second protruding members spaced apart from each other on the pad region; a source-drain pattern disposed on the interlayer insulating layer and including at least a portion electrically connected to the semiconductor pattern; a via layer covering the source-drain pattern, and A light emitting diode arranged on the through hole layer, Wherein each of the first protruding members extends along at least a portion of an outer boundary of the footprint, Each of the second protruding members extends along at least a portion of an outer boundary of the pad region, and The number of the first protruding members and the number of the second protruding members are different from each other.

Description

Display panel and electronic device comprising same The present application claims priority and ownership rights obtained from korean patent application No. 10-2024-0153833 filed on 1 month 11 of 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field The present disclosure relates to a display panel configured to prevent defects caused by crack propagation and an electronic device including the display panel. Background Display panels and electronic devices incorporating the same typically include a plurality of light emitting diodes to provide images to a user. Further, wiring for controlling the plurality of light emitting diodes is arranged on the display panel. Disclosure of Invention During use of the electronic device by a user, various forms of impact may be applied to the display panel. Accordingly, a crack may occur in the display panel, and if the crack propagates to the aforementioned wiring, the wiring may become exposed to the outside. The exposed wiring is susceptible to corrosion, and such corrosion may cause malfunction of the display panel. In particular, when a crack occurs in a region where more wiring is concentrated, the possibility of failure due to crack propagation increases. The vulnerability of the display panel to failure caused by crack propagation may vary depending on the specific area of the display panel. Features of the present disclosure provide a display panel capable of effectively preventing defects caused by crack propagation by designing crack dams in a differentiated manner according to regions, and an electronic device having the same. The display panel in the embodiments of the present disclosure may include a base substrate, a semiconductor pattern, a gate insulating layer, a gate pattern, an interlayer insulating layer, a source-drain pattern, a via layer, and a light emitting diode. A first region and a second region may be defined in the base substrate. The second region may include a bending region, a covering region, and a pad region. The bending zone may be bendable. The footprint may extend from one side of the curved region and may surround the first region. The pad region may extend from an opposite side of the bending region to the one side of the bending region. The semiconductor pattern may be disposed on the first region, and may include a semiconductor material. The gate insulating layer may be disposed on the base substrate and may cover the semiconductor pattern. The gate pattern may be disposed on the gate insulating layer, wherein at least a portion thereof overlaps the semiconductor pattern. The interlayer insulating layer may cover the gate pattern. A plurality of first crack stop openings are defined in a portion of the interlayer insulating layer overlapping the footprint, and a plurality of second crack stop openings are defined in a portion of the interlayer insulating layer overlapping the pad region. Each of the plurality of first crack stop openings may extend along an outer edge of the footprint and each of the plurality of second crack stop openings may extend along an outer edge of the pad region. The number of the plurality of first crack stop openings and the number of the plurality of second crack stop openings may be different from each other. The source-drain pattern may be disposed on the interlayer insulating layer, wherein at least a portion thereof is electrically connected to the semiconductor pattern. The via layer may cover the source-drain pattern, and the light emitting diode may be disposed on the via layer. In embodiments of the present disclosure, the number of the plurality of second crack stop openings may be greater than the number of the plurality of first crack stop openings. In an embodiment of the present disclosure, at least one of the plurality of third crack stop openings and the plurality of fourth crack stop openings may be defined in the gate insulating layer. The plurality of third crack stop openings may overlap the first crack stop openings, respectively. The plurality of fourth crack stop openings may overlap the second crack stop openings, respectively. The display panel in the embodiments of the present disclosure may further include a plurality of pads, an electrical component, and a plurality of spider wiring lines. A plurality of pads may be arranged on the pad region. The electrical component may overlap with the plurality of pads. The plurality of spider wiring lines may extend from the plurality of pads, respectively, and transmit signals from the electrical component to at least one of the source-drain pattern and the gate pattern. A plurality of second crack stop openings may be defined between the plurality of spider wiring lines and the outer edge of the pad region. In an embodiment of the present disclosure, the plurality of second crack stop openings may be spaced apart from the plurality of first crack stop openings across the bending zone in