CN-122003034-A - Display panel and display device

Abstract

The application discloses a display panel and a display device, wherein a first metal layer is arranged on a substrate, the first metal layer comprises a plurality of first grid electrodes which are arranged at intervals, the first grid electrodes are configured as bottom grid electrodes of transistors, and a voltage difference exists between two adjacent first grid electrodes in the same period. The first grid electrode comprises a first metal part and a second metal part, wherein the second metal part is arranged on one side of the first metal part far away from the substrate, and the material of the first metal part is metal which forms a passivation film on the surface of the first metal part under the standard oxidation potential. According to the embodiment of the application, the material of the first metal part is metal which can form the passivation layer on the surface of the first metal part, namely the material of the first metal part is self-passivation metal, and when the first metal part is oxidized to form the passivation film on the surface of the first metal part, the passivation film can reduce the risk of electrochemical oxidation corrosion of the internal metal of the first metal part, and the stability of the thin film transistor is improved.

Inventors

• SHU MIN
• ZHANG HUANXI
• ZHOU XINGYU
• ZHAO LEI

Assignees

• 武汉华星光电半导体显示技术有限公司

Dates

Publication Date

20260508

Application Date

20260226

Claims (13)

1. 1. A display panel, comprising: A substrate; The first metal layer is arranged on the substrate and comprises a plurality of first grid electrodes which are arranged at intervals, the first grid electrodes are configured as bottom grid electrodes of transistors, and a voltage difference exists between two adjacent first grid electrodes in the same period; the first grid electrode comprises a first metal part and a second metal part, the second metal part is arranged on one side, far away from the substrate, of the first metal part, and the material of the first metal part is metal capable of forming a passivation film on the surface of the first metal part.
2. 2. The display panel of claim 1, wherein the display panel comprises a gate drive circuit comprising a fifth transistor and a sixth transistor, the gate of the fifth transistor comprising a first gate, the first gate of the fifth transistor configured as a fifth bottom gate, the gate of the sixth transistor comprising a first gate, the first gate of the sixth transistor configured as a sixth bottom gate, the fifth bottom gate being connected to one of a high level and a low level, the sixth bottom gate being connected to the other of the high level and the low level during a same period; In the display panel under the overlook visual angle, the sixth bottom grid is located one side of the fifth bottom grid and is arranged adjacent to the fifth bottom grid, the fifth bottom grid comprises a connecting portion and a plurality of first sub-portions, the connecting portion is connected to one side of the first sub-portions, the first sub-portions are arranged at intervals along the length direction of the connecting portion, the sixth bottom grid comprises a second sub-portion, and in the length direction of the connecting portion, the second sub-portion is located at one side of the first sub-portion.
3. 3. The display panel according to claim 2, wherein a distance between the second sub-portion and the fifth bottom gate is greater than a distance between adjacent two of the first sub-portions in a length direction of the connection portion.
4. 4. The display panel of claim 2, wherein the gate driving circuit comprises a second transistor, the gate of the second transistor comprising a first gate, the first gate of the second transistor configured as a second bottom gate; in the same period, the second bottom gate and the fifth bottom gate access the same level signal, and the second bottom gate and the sixth bottom gate access different level signals; In the display panel in a top view, in the length direction of the first sub-portion, the second bottom gate is spaced at one side of the connection portion, in the length direction of the connection portion, the second bottom gate extends to protrude from the fifth bottom gate, the sixth bottom gate includes a surrounding portion, in the length direction of the second sub-portion, the surrounding portion is connected to one side of the second sub-portion, and the surrounding portion is disposed around the periphery of the second bottom gate.
5. 5. The display panel of claim 4, wherein the gate driving circuit comprises a fourth transistor, the gate of the fourth transistor comprising a first gate, the first gate of the fourth transistor configured as a fourth bottom gate, the fourth bottom gate configured to always be connected to the low level; in the display panel in a top view, the fourth bottom gate is located on one side of the fifth bottom gate in a longitudinal direction of the first sub-portion, and a portion of the fourth bottom gate is aligned with the surrounding portion in the longitudinal direction of the connecting portion.
6. 6. The display panel according to claim 5, wherein a distance from a portion of the fourth bottom gate aligned with the surrounding portion to the surrounding portion is greater than a distance from adjacent two of the first sub-portions in a length direction of the connection portion.
7. 7. The display panel according to claim 5, wherein a length direction of a portion of the second bottom gate adjacent to the fifth bottom gate is perpendicular to a length direction of the connecting portion.
8. 8. The display panel according to any one of claims 1-7, wherein a ratio of a thickness of the second metal portion to a thickness of the first metal portion is between 1/10 and 1/2.
9. 9. The display panel of any one of claims 1-7, wherein the orthographic projection of the second metal portion onto the substrate is disposed within the orthographic projection of the first metal portion onto the substrate.
10. 10. The display panel according to any one of claims 1 to 7, wherein a material of the first metal portion is selected from at least one of titanium, zirconium, tantalum, and niobium.
11. 11. The display panel of any one of claims 1-7, wherein the display panel comprises a barrier layer disposed between the substrate and the first gate electrode; The barrier layer comprises a first sub-layer and a second sub-layer which are stacked, the first grid electrode is arranged on one side, far away from the first sub-layer, of the second sub-layer, and the density of the second sub-layer is larger than that of the first sub-layer.
12. 12. The display panel of any one of claims 1-7, further comprising an active layer and a second metal layer, wherein the active layer is located on a side of the first metal layer away from the substrate, the second metal layer is located on a side of the active layer away from the first metal layer, the second metal layer comprises a plurality of second gates disposed at intervals, the second gates are configured as top gates of the transistors, one of the second gates is correspondingly connected to one of the first gates to form a gate of the transistor, and the semiconductor material of the active layer is a silicon-based semiconductor.
13. 13. A display device comprising a display panel according to any one of claims 1-12.

Description

Display panel and display device Technical Field The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background In an organic light emitting diode display panel, low power consumption is one of important customer requirements, and in order to improve the performance of a thin film transistor, a top-bottom double-gate design can be matched. In the design of the top and bottom double grids of the thin film transistor, the double grids are connected to the same electric signal, and because of the high-low potential difference existing between the bottom grids of the partially adjacent thin film transistors when the display panel works, when the display panel is in a high-temperature and high-humidity environment, water vapor can invade the inside of the panel through the edges of the cutting channels, electrochemical corrosion is easy to occur as bottom grid metal in the grid driving circuit at the edge of the panel under the action of the water vapor and the voltage difference, and the problems of split screen, even black spots and the like of the display panel are caused. Disclosure of Invention The embodiment of the application provides a display panel and a display device, which aim to at least partially solve the technical problems. In order to achieve the above object, according to a first aspect of the present application, there is provided a display panel comprising: A substrate; The first metal layer is arranged on the substrate and comprises a plurality of first grid electrodes which are arranged at intervals, the first grid electrodes are configured as bottom grid electrodes of transistors, and a voltage difference exists between two adjacent first grid electrodes in the same period; the first grid electrode comprises a first metal part and a second metal part, the second metal part is arranged on one side, far away from the substrate, of the first metal part, and the material of the first metal part is metal capable of forming a passivation film on the surface of the first metal part. Optionally, in some embodiments of the present application, the display panel includes a gate driving circuit including a fifth transistor and a sixth transistor, the gate of the fifth transistor including a first gate, the first gate of the fifth transistor being configured as a fifth bottom gate, the gate of the sixth transistor including a first gate, the first gate of the sixth transistor being configured as a sixth bottom gate, the fifth bottom gate being connected to one of a high level and a low level, the sixth bottom gate being connected to the other of the high level and the low level during a same period; In the display panel under the overlook visual angle, the sixth bottom grid is located one side of the fifth bottom grid and is arranged adjacent to the fifth bottom grid, the fifth bottom grid comprises a connecting portion and a plurality of first sub-portions, the connecting portion is connected to one side of the first sub-portions, the first sub-portions are arranged at intervals along the length direction of the connecting portion, the sixth bottom grid comprises a second sub-portion, and in the length direction of the connecting portion, the second sub-portion is located at one side of the first sub-portion. Optionally, in some embodiments of the present application, a distance between the second sub-portion and the fifth bottom gate is greater than a distance between two adjacent first sub-portions in a length direction of the connection portion. Optionally, in some embodiments of the present application, the gate driving circuit includes a second transistor, a gate of the second transistor includes a first gate, and the first gate of the second transistor is configured as a second bottom gate; in the same period, the second bottom gate and the fifth bottom gate access the same level signal, and the second bottom gate and the sixth bottom gate access different level signals; In the display panel in a top view, in the length direction of the first sub-portion, the second bottom gate is spaced at one side of the connection portion, in the length direction of the connection portion, the second bottom gate extends to protrude from the fifth bottom gate, the sixth bottom gate includes a surrounding portion, in the length direction of the second sub-portion, the surrounding portion is connected to one side of the second sub-portion, and the surrounding portion is disposed around the periphery of the second bottom gate. Optionally, in some embodiments of the present application, the gate driving circuit includes a fourth transistor, a gate of the fourth transistor includes a first gate, and the first gate of the fourth transistor is configured as a fourth bottom gate; in the display panel in a top view, the fourth bottom gate is located on one side of the fifth bottom gate in a longitudinal direction of the first sub-portion, an