CN-122003104-A - Gate tube, method for manufacturing gate tube, chip, electronic component and electronic equipment

Abstract

The embodiment of the application provides a gate tube, a method for manufacturing the gate tube, a chip, an electronic assembly and electronic equipment. The gate tube comprises a first electrode, a second electrode, a plurality of dielectric layers and a first isolation layer. The plurality of dielectric layers are located between the first electrode and the second electrode and include a first dielectric layer and a second dielectric layer. The second dielectric layer surrounds the first dielectric layer. The first isolation layer is disposed between the first dielectric layer and the second dielectric layer. The gate tube comprises a plurality of medium layers, so that the ratio of the perimeter of the medium layer of the gate tube relative to the sectional area and the area of the side wall can be increased, the fringe electric field is increased, the current density of the gate tube is increased, and the nonlinearity is increased. Through making first isolation layer arrange between first dielectric layer and second dielectric layer, can carry out the electric isolation to first dielectric layer and second dielectric layer, protect this increase fringe electric field to effectively increase the nonlinearity of gate tube, improve the performance of gate tube.

Inventors

• SHI JIACHENG
• CHEN RUI
• ZHANG QIANG
• Gan Weizhuo
• ZHAO CHUNSONG

Assignees

• 华为技术有限公司

Dates

Publication Date

20260508

Application Date

20260206

Claims (20)

1. 1. The utility model provides a gate tube which characterized in that includes: A first electrode; a second electrode; a plurality of dielectric layers between the first electrode and the second electrode, wherein the plurality of dielectric layers comprises: A first dielectric layer, and A second dielectric layer surrounding the first dielectric layer, and A first isolation layer is disposed between the first dielectric layer and the second dielectric layer.
2. 2. The gate tube of claim 1, wherein the first isolation layer comprises at least one of a passivation layer, an air layer, or a combination of a passivation layer and an air layer.
3. 3. The gate tube of claim 1 or 2, wherein the thickness of the first isolation layer is less than 5nm, or the thickness of the first isolation layer is less than 2nm, or the thickness of the first isolation layer is less than 1nm.
4. 4. The gate tube of any one of claims 1-3, wherein a thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or a thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 80:1, or a thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 100:1.
5. 5. The gate tube of any one of claims 1-4, wherein the first dielectric layer and the second dielectric layer comprise the same dielectric material.
6. 6. The gate tube of any one of claims 1-5, wherein the first dielectric layer or the second dielectric layer comprises a single dielectric material or multiple dielectric materials.
7. 7. The gate tube of claim 5 or 6, wherein the dielectric material is selected from at least one of ：Ta 2 O 5 、HfO 2 、TiO 2 、ZrO、SiO 2 、aSi、Al 2 O 3 、HfSiO 4 、ZrSiO 4 、La 2 O 3 、Y 2 O 3 、ZnO、NiO、 or MgO.
8. 8. The gate tube of any one of claims 1-7, wherein the first electrode and the second electrode comprise the same metallic material or different metallic materials.
9. 9. The gate tube of claim 8, wherein the first electrode or the second electrode comprises a metallic material or alloy thereof selected from at least one of Pt, ti, tiN, taN, tiAl, pd, ir, W, ta or Ru.
10. 10. The gate tube of any one of claims 2-9, wherein the passivation layer is made of a material selected from at least one of SiNx or SiON.
11. 11. The gate tube of any one of claims 1-10, wherein the plurality of dielectric layers further comprises: a third dielectric layer surrounding the second dielectric layer, Wherein the gate tube further comprises: a second isolation layer is disposed between the second dielectric layer and the third dielectric layer.
12. 12. The gate tube of claim 11, wherein the third dielectric layer has the same dielectric material as the first dielectric layer and the second dielectric layer.
13. 13. The gate tube of claim 11 or 12, wherein the thickness of the second isolation layer is less than 5nm, or the thickness of the second isolation layer is less than 2nm, or the thickness of the second isolation layer is less than 1nm.
14. 14. The gate tube of any one of claims 1-13, wherein in a cross-section of the plurality of dielectric layers parallel to the first electrode or the second electrode, the first dielectric layer, the first spacer layer, and the second dielectric layer are one of concentric circles, concentric ovals, or concentric polygons.
15. 15. The gate of any one of claims 1-14, wherein the gate is configured such that a voltage between the first electrode and the second electrode has a non-linear relationship with a current flowing through the gate.
16. 16. A method for manufacturing a gate tube, comprising: Forming a first electrode; Forming a second electrode; Forming a plurality of dielectric layers between the first electrode and the second electrode, wherein forming the plurality of dielectric layers comprises: Forming a first dielectric layer, and Forming a second dielectric layer surrounding the first dielectric layer, and And forming a first isolation layer, wherein the first isolation layer is positioned between the first dielectric layer and the second dielectric layer.
17. 17. The method of claim 16, wherein forming a first dielectric layer comprises: Depositing a dielectric material on the first electrode to form an initial first dielectric layer, and And etching the peripheral part of the initial first dielectric layer to form the first dielectric layer.
18. 18. The method of claim 17, wherein forming a first isolation layer comprises: forming the first isolation layer around the first dielectric layer, Wherein forming the second dielectric layer comprises: forming the second dielectric layer around the first isolation layer, Wherein forming the second electrode comprises: and forming the second electrode on the first dielectric layer, the first isolation layer and the second dielectric layer.
19. 19. The method of claim 17, wherein forming a second electrode comprises: Forming the second electrode on the initial first dielectric layer before etching the outer peripheral portion of the initial first dielectric layer, Wherein forming the first isolation layer comprises: After etching the outer peripheral portion of the initial first dielectric layer, forming the first isolation layer around the first dielectric layer, Wherein forming the second dielectric layer comprises: and forming the second dielectric layer around the first isolation layer.
20. 20. The method of any of claims 16-19, wherein the thickness of the first spacer is less than 5nm, or the thickness of the first spacer is less than 2nm, or the thickness of the first spacer is less than 1nm.

Description

Gate tube, method for manufacturing gate tube, chip, electronic component and electronic equipment Technical Field Embodiments of the present application relate generally to the field of semiconductors, and more particularly, to a gate tube, a method for manufacturing a gate tube, a chip, an electronic assembly, and an electronic device. Background With the continuous development of semiconductor technology, nonlinear semiconductor devices are increasingly used. For example, a gate tube as a nonlinear device exhibits different resistance values at different voltages, and a current flowing through the gate tube has a nonlinear relationship with a voltage applied to the gate tube. The gate tube can be applied to an environment which is selectively switched on according to voltage so as to relieve leakage current or crosstalk in the application environment. Therefore, a gate tube having a large degree of nonlinearity is desired. Disclosure of Invention The embodiment of the application provides a technical scheme of a gate tube with improved nonlinearity, so as to realize improved performance of the gate tube. According to a first aspect, a gate tube is provided. The gate tube can be a gate tube for any electronic equipment. For example, the gate tube may be used for any type of chip of an electronic device, such as a control type chip, a memory type chip, an analog type chip, a communication type chip, or a logic type chip. The gate tube comprises a first electrode, a second electrode, a plurality of dielectric layers and a first isolation layer. A plurality of dielectric layers are positioned between the first electrode and the second electrode. The plurality of dielectric layers includes a first dielectric layer and a second dielectric layer. The second dielectric layer surrounds the first dielectric layer. The first isolation layer is disposed between the first dielectric layer and the second dielectric layer. The gate tube comprises a plurality of medium layers, so that the ratio of the perimeter of the medium layer of the gate tube to the cross section area can be increased, the area of the side wall is increased, and the fringe electric field is increased. Along with the increase of the fringe electric field, the current density of the gate tube is also increased, so that the nonlinearity of the gate tube is increased. The first dielectric layer and the second dielectric layer can be electrically isolated by arranging the first isolation layer of the gate tube between the first dielectric layer and the second dielectric layer in the plurality of dielectric layers, so that the increased fringe electric field is protected. Through the protection, the current density of the gate tube can be effectively increased, so that the nonlinearity of the gate tube is effectively increased, and the performance of the gate tube is effectively improved. In some implementations, the first isolation layer includes at least one of a passivation layer, an air layer, or a combination of a passivation layer and an air layer. Therefore, the first isolation layer can be realized in different structures according to actual needs, and the design flexibility of the gate tube is improved. In some implementations, the thickness of the first isolation layer is less than 5nm, or the thickness of the first isolation layer is less than 2nm, or the thickness of the first isolation layer is less than 1nm. Therefore, the thickness of the first isolation layer can be smaller while the first isolation layer is used for realizing electric isolation of the first dielectric layer and the second dielectric layer. The first isolation layer with smaller thickness has smaller influence on the current density of the gate tube and can be even ignored. Therefore, the nonlinearity of the gate tube can be further effectively increased, and the performance of the gate tube can be effectively improved. In some implementations, the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 50:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 80:1, or the thickness ratio of the first dielectric layer or the second dielectric layer to the first isolation layer is greater than 100:1. Therefore, the first isolation layer can realize electrical isolation of the first dielectric layer and the second dielectric layer, and meanwhile the sectional area of the first isolation layer is smaller than the whole sectional area of the plurality of dielectric layers. The smaller duty ratio can make the influence of the arrangement of the first isolation layer on the current flowing through the gate tube smaller and even negligible. Therefore, the nonlinearity of the gate tube can be further effectively increased, and the performance of the gate tube can be effectively improved. In some implementations, the first dielectric layer