CN-122003129-A - Semiconductor chip and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor chip and a method for manufacturing the same, which belong to the field of semiconductor devices. The semiconductor chip comprises an epitaxial layer, a passivation layer and a cutting path reflecting layer, wherein the epitaxial layer is provided with an isolation groove, the passivation layer covers one side of the epitaxial layer and fills the isolation groove, and the cutting path reflecting layer covers one side of the passivation layer and corresponds to the isolation groove. The method and the device can effectively improve the crack detection efficiency and accuracy of the semiconductor chip.

Inventors

• LI HAOMIN
• JIANG KE
• TANG MIAO

Assignees

• 京东方华灿光电(广东)有限公司

Dates

Publication Date

20260508

Application Date

20251218

Claims (10)

1. 1. The semiconductor chip is characterized by comprising an epitaxial layer (10), a passivation layer (20) and a dicing street reflecting layer (30); The epitaxial layer (10) has an isolation trench (40); the passivation layer (20) covers one side of the epitaxial layer (10) and fills the isolation trench (40); the scribe line reflective layer (30) covers one side of the passivation layer (20) and corresponds to the location of the isolation trench (40).
2. 2. The semiconductor chip according to claim 1, wherein the isolation trench (40) has a marker (50) therein; the scribe line light reflective layer (30) has a hole (310), the hole (310) being opposite to the mark point (50) to expose the mark point (50).
3. 3. A semiconductor chip according to claim 2, characterized in that the marker point (50) is located at the intersection between two of the isolation trenches (40).
4. 4. The semiconductor chip according to claim 1, wherein the dicing street light reflecting layer (30) has a thickness of 1 to 10 μm.
5. 5. The semiconductor chip according to claim 1, characterized in that the orthographic projection of the scribe line reflective layer (30) on the plane of the epitaxial layer (10) is located within the isolation trench (40).
6. 6. A method of manufacturing a semiconductor chip, comprising: preparing an epitaxial layer (10), and etching an isolation trench (40) on the epitaxial layer (10); -preparing a passivation layer (20) on one side of the epitaxial layer (10), the passivation layer (20) filling the isolation trench (40); preparing a cut-line reflective layer (30) on one side of the passivation layer (20), the cut-line reflective layer (30) being located at a position corresponding to the isolation trench (40); Performing splitting operation along the cut-way reflective layer (30); And performing automatic optical detection to judge whether the cutting-path reflecting layer (30) has a crack trace, if the cutting-path reflecting layer (30) has the crack trace, the crack operation at the corresponding position is successful, and if the cutting-path reflecting layer (30) does not have the crack trace, the crack operation at the corresponding position is failed.
7. 7. The method of manufacturing according to claim 6, characterized in that preparing an epitaxial layer (10) and etching an isolation trench (40) on the epitaxial layer (10) comprises: during etching of the isolation trenches (40), a marker (50) is formed at the intersection of two of the isolation trenches (40).
8. 8. The method of manufacturing according to claim 7, wherein manufacturing a scribe line reflective layer (30) on one side of the passivation layer (20) comprises: Coating a black glue on one side of the passivation layer (20); and photoetching the black glue to obtain the cutting path reflecting layer (30), wherein the cutting path reflecting layer (30) is provided with holes (310), and the holes (310) are opposite to the mark points (50) so as to expose the mark points (50).
9. 9. The method of manufacturing according to claim 6, characterized in that after manufacturing a cut-way reflective layer (30) on one side of the passivation layer (20), the method of manufacturing comprises: Etching the cutting path reflecting layer (30) to thin the thickness of the cutting path reflecting layer (30) to 1-10 mu m; the cut-out light-reflecting layer (30) is immersed in an organic solution.
10. 10. The method of manufacturing according to claim 6, wherein automated optical inspection is performed, comprising: Respectively shooting to obtain a light-emitting surface gray-scale image and an electrode surface gray-scale image of the semiconductor chip; Checking whether the positions of the luminous surface gray level diagram and the electrode surface gray level diagram, which correspond to the cutting channel reflecting layer (30), have crack marks or not; If the luminous surface gray level diagram and the electrode surface gray level diagram are provided with the splitting marks, the splitting operation at the corresponding position is successful, and if the luminous surface gray level diagram or the electrode surface gray level diagram is not provided with the splitting marks, the splitting operation at the corresponding position is failed.

Description

Semiconductor chip and method for manufacturing the same Technical Field The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor chip and a method for manufacturing the same. Background Semiconductor chips, a common type of functional electronic device, are widely used in various subdivision areas. In the related art, in order to better show the scribe line, the residual photoresist outside the isolation trench is removed to facilitate the breaking operation in the subsequent process. However, such design can lead to unsuccessful splinter areas, which can only be detected manually, thus not only wasting labor cost, but also having low efficiency and low accuracy. Disclosure of Invention The embodiment of the disclosure provides a semiconductor chip and a preparation method thereof, which can effectively improve the crack detection efficiency and accuracy of the semiconductor chip. The technical scheme is as follows: in a first aspect, embodiments of the present disclosure provide a semiconductor chip including an epitaxial layer, a passivation layer, and a scribe line reflective layer; The epitaxial layer is provided with an isolation trench; The passivation layer covers one side of the epitaxial layer and fills the isolation trench; The cutting path reflecting layer covers one side of the passivation layer and corresponds to the isolation groove. In one implementation of the present disclosure, the isolation trench has a marker point therein; the cut-way reflective layer is provided with a hole, and the hole is opposite to the mark point so as to expose the mark point. In one implementation of the present disclosure, the marker point is located at an intersection between two of the isolation trenches. In one implementation of the disclosure, the thickness of the reflective layer of the dicing street is 1-10 μm. In one implementation of the present disclosure, the orthographic projection of the scribe line reflective layer on the plane of the epitaxial layer is located within the isolation trench. In a second aspect, embodiments of the present disclosure provide a method for manufacturing a semiconductor chip, the method including: preparing an epitaxial layer, and etching an isolation groove on the epitaxial layer; Preparing a passivation layer on one side of the epitaxial layer, wherein the passivation layer fills the isolation trench; Preparing a cutting path reflecting layer on one side of the passivation layer, wherein the cutting path reflecting layer is positioned at a position corresponding to the isolation groove; performing splitting operation along the cutting path reflecting layer; and performing automatic optical detection to judge whether the cutting-path reflecting layer has a split trace, if the cutting-path reflecting layer has the split trace, the split operation at the corresponding position is successful, and if the cutting-path reflecting layer does not have the split trace, the split operation at the corresponding position fails. In one implementation of the present disclosure, preparing an epitaxial layer and etching an isolation trench on the epitaxial layer includes: and forming a mark point at the intersection of the two isolation trenches in the process of etching the isolation trenches. In one implementation of the present disclosure, preparing a scribe line reflective layer on one side of the passivation layer includes: Coating black glue on one side of the passivation layer; And photoetching the black glue to obtain the cutting path reflecting layer, wherein the cutting path reflecting layer is provided with holes, and the holes are opposite to the mark points so as to expose the mark points. In one implementation of the present disclosure, after preparing a scribe line reflective layer on one side of the passivation layer, the preparation method includes: etching the cutting path reflecting layer to thin the thickness of the cutting path reflecting layer to 1-10 mu m; And soaking the cut-way reflecting layer by using an organic solution. In one implementation of the present disclosure, an automated optical inspection is performed, comprising: Respectively shooting to obtain a light-emitting surface gray-scale image and an electrode surface gray-scale image of the semiconductor chip; checking whether the positions of the light-emitting surface gray level diagram and the electrode surface gray level diagram, which correspond to the cutting channel reflecting layer, have crack marks or not; If the luminous surface gray level diagram and the electrode surface gray level diagram are provided with the splitting marks, the splitting operation at the corresponding position is successful, and if the luminous surface gray level diagram or the electrode surface gray level diagram is not provided with the splitting marks, the splitting operation at the corresponding position is failed. The technical scheme provided by the embodiment of the disclo